mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-26 06:04:14 +08:00
7c0f6ba682
This was entirely automated, using the script by Al:
PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*<asm/uaccess.h>'
sed -i -e "s!$PATT!#include <linux/uaccess.h>!" \
$(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)
to do the replacement at the end of the merge window.
Requested-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
585 lines
12 KiB
C
585 lines
12 KiB
C
/*
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* align.c - address exception handler for M32R
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*
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* Copyright (c) 2003 Hitoshi Yamamoto
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*/
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#include <asm/ptrace.h>
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#include <linux/uaccess.h>
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static int get_reg(struct pt_regs *regs, int nr)
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{
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int val;
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if (nr < 4)
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val = *(unsigned long *)(®s->r0 + nr);
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else if (nr < 7)
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val = *(unsigned long *)(®s->r4 + (nr - 4));
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else if (nr < 13)
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val = *(unsigned long *)(®s->r7 + (nr - 7));
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else
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val = *(unsigned long *)(®s->fp + (nr - 13));
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return val;
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}
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static void set_reg(struct pt_regs *regs, int nr, int val)
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{
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if (nr < 4)
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*(unsigned long *)(®s->r0 + nr) = val;
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else if (nr < 7)
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*(unsigned long *)(®s->r4 + (nr - 4)) = val;
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else if (nr < 13)
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*(unsigned long *)(®s->r7 + (nr - 7)) = val;
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else
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*(unsigned long *)(®s->fp + (nr - 13)) = val;
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}
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#define REG1(insn) (((insn) & 0x0f00) >> 8)
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#define REG2(insn) ((insn) & 0x000f)
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#define PSW_BC 0x100
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/* O- instruction */
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#define ISA_LD1 0x20c0 /* ld Rdest, @Rsrc */
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#define ISA_LD2 0x20e0 /* ld Rdest, @Rsrc+ */
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#define ISA_LDH 0x20a0 /* ldh Rdest, @Rsrc */
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#define ISA_LDUH 0x20b0 /* lduh Rdest, @Rsrc */
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#define ISA_ST1 0x2040 /* st Rsrc1, @Rsrc2 */
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#define ISA_ST2 0x2060 /* st Rsrc1, @+Rsrc2 */
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#define ISA_ST3 0x2070 /* st Rsrc1, @-Rsrc2 */
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#define ISA_STH1 0x2020 /* sth Rsrc1, @Rsrc2 */
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#define ISA_STH2 0x2030 /* sth Rsrc1, @Rsrc2+ */
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#ifdef CONFIG_ISA_DUAL_ISSUE
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/* OS instruction */
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#define ISA_ADD 0x00a0 /* add Rdest, Rsrc */
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#define ISA_ADDI 0x4000 /* addi Rdest, #imm8 */
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#define ISA_ADDX 0x0090 /* addx Rdest, Rsrc */
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#define ISA_AND 0x00c0 /* and Rdest, Rsrc */
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#define ISA_CMP 0x0040 /* cmp Rsrc1, Rsrc2 */
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#define ISA_CMPEQ 0x0060 /* cmpeq Rsrc1, Rsrc2 */
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#define ISA_CMPU 0x0050 /* cmpu Rsrc1, Rsrc2 */
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#define ISA_CMPZ 0x0070 /* cmpz Rsrc */
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#define ISA_LDI 0x6000 /* ldi Rdest, #imm8 */
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#define ISA_MV 0x1080 /* mv Rdest, Rsrc */
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#define ISA_NEG 0x0030 /* neg Rdest, Rsrc */
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#define ISA_NOP 0x7000 /* nop */
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#define ISA_NOT 0x00b0 /* not Rdest, Rsrc */
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#define ISA_OR 0x00e0 /* or Rdest, Rsrc */
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#define ISA_SUB 0x0020 /* sub Rdest, Rsrc */
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#define ISA_SUBX 0x0010 /* subx Rdest, Rsrc */
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#define ISA_XOR 0x00d0 /* xor Rdest, Rsrc */
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/* -S instruction */
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#define ISA_MUL 0x1060 /* mul Rdest, Rsrc */
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#define ISA_MULLO_A0 0x3010 /* mullo Rsrc1, Rsrc2, A0 */
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#define ISA_MULLO_A1 0x3090 /* mullo Rsrc1, Rsrc2, A1 */
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#define ISA_MVFACMI_A0 0x50f2 /* mvfacmi Rdest, A0 */
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#define ISA_MVFACMI_A1 0x50f6 /* mvfacmi Rdest, A1 */
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static int emu_addi(unsigned short insn, struct pt_regs *regs)
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{
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char imm = (char)(insn & 0xff);
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int dest = REG1(insn);
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int val;
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val = get_reg(regs, dest);
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val += imm;
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_ldi(unsigned short insn, struct pt_regs *regs)
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{
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char imm = (char)(insn & 0xff);
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set_reg(regs, REG1(insn), (int)imm);
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return 0;
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}
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static int emu_add(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int src = REG2(insn);
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int val;
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val = get_reg(regs, dest);
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val += get_reg(regs, src);
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_addx(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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unsigned int val, tmp;
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val = regs->psw & PSW_BC ? 1 : 0;
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tmp = get_reg(regs, dest);
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val += tmp;
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val += (unsigned int)get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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/* C bit set */
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if (val < tmp)
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_and(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int val;
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val = get_reg(regs, dest);
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val &= get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_cmp(unsigned short insn, struct pt_regs *regs)
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{
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if (get_reg(regs, REG1(insn)) < get_reg(regs, REG2(insn)))
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_cmpeq(unsigned short insn, struct pt_regs *regs)
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{
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if (get_reg(regs, REG1(insn)) == get_reg(regs, REG2(insn)))
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_cmpu(unsigned short insn, struct pt_regs *regs)
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{
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if ((unsigned int)get_reg(regs, REG1(insn))
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< (unsigned int)get_reg(regs, REG2(insn)))
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_cmpz(unsigned short insn, struct pt_regs *regs)
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{
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if (!get_reg(regs, REG2(insn)))
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_mv(unsigned short insn, struct pt_regs *regs)
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{
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int val;
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val = get_reg(regs, REG2(insn));
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set_reg(regs, REG1(insn), val);
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return 0;
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}
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static int emu_neg(unsigned short insn, struct pt_regs *regs)
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{
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int val;
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val = get_reg(regs, REG2(insn));
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set_reg(regs, REG1(insn), 0 - val);
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return 0;
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}
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static int emu_not(unsigned short insn, struct pt_regs *regs)
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{
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int val;
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val = get_reg(regs, REG2(insn));
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set_reg(regs, REG1(insn), ~val);
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return 0;
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}
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static int emu_or(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int val;
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val = get_reg(regs, dest);
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val |= get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_sub(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int val;
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val = get_reg(regs, dest);
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val -= get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_subx(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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unsigned int val, tmp;
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val = tmp = get_reg(regs, dest);
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val -= (unsigned int)get_reg(regs, REG2(insn));
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val -= regs->psw & PSW_BC ? 1 : 0;
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set_reg(regs, dest, val);
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/* C bit set */
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if (val > tmp)
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_xor(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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unsigned int val;
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val = (unsigned int)get_reg(regs, dest);
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val ^= (unsigned int)get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_mul(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int reg1, reg2;
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reg1 = get_reg(regs, dest);
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reg2 = get_reg(regs, REG2(insn));
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__asm__ __volatile__ (
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"mul %0, %1; \n\t"
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: "+r" (reg1) : "r" (reg2)
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);
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set_reg(regs, dest, reg1);
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return 0;
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}
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static int emu_mullo_a0(unsigned short insn, struct pt_regs *regs)
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{
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int reg1, reg2;
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reg1 = get_reg(regs, REG1(insn));
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reg2 = get_reg(regs, REG2(insn));
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__asm__ __volatile__ (
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"mullo %0, %1, a0; \n\t"
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"mvfachi %0, a0; \n\t"
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"mvfaclo %1, a0; \n\t"
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: "+r" (reg1), "+r" (reg2)
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);
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regs->acc0h = reg1;
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regs->acc0l = reg2;
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return 0;
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}
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static int emu_mullo_a1(unsigned short insn, struct pt_regs *regs)
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{
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int reg1, reg2;
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reg1 = get_reg(regs, REG1(insn));
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reg2 = get_reg(regs, REG2(insn));
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__asm__ __volatile__ (
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"mullo %0, %1, a0; \n\t"
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"mvfachi %0, a0; \n\t"
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"mvfaclo %1, a0; \n\t"
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: "+r" (reg1), "+r" (reg2)
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);
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regs->acc1h = reg1;
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regs->acc1l = reg2;
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return 0;
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}
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static int emu_mvfacmi_a0(unsigned short insn, struct pt_regs *regs)
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{
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unsigned long val;
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val = (regs->acc0h << 16) | (regs->acc0l >> 16);
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set_reg(regs, REG1(insn), (int)val);
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return 0;
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}
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static int emu_mvfacmi_a1(unsigned short insn, struct pt_regs *regs)
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{
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unsigned long val;
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val = (regs->acc1h << 16) | (regs->acc1l >> 16);
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set_reg(regs, REG1(insn), (int)val);
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return 0;
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}
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static int emu_m32r2(unsigned short insn, struct pt_regs *regs)
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{
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int res = -1;
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if ((insn & 0x7fff) == ISA_NOP) /* nop */
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return 0;
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switch(insn & 0x7000) {
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case ISA_ADDI: /* addi Rdest, #imm8 */
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res = emu_addi(insn, regs);
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break;
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case ISA_LDI: /* ldi Rdest, #imm8 */
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res = emu_ldi(insn, regs);
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break;
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default:
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break;
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}
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if (!res)
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return 0;
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switch(insn & 0x70f0) {
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case ISA_ADD: /* add Rdest, Rsrc */
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res = emu_add(insn, regs);
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break;
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case ISA_ADDX: /* addx Rdest, Rsrc */
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res = emu_addx(insn, regs);
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break;
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case ISA_AND: /* and Rdest, Rsrc */
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res = emu_and(insn, regs);
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break;
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case ISA_CMP: /* cmp Rsrc1, Rsrc2 */
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res = emu_cmp(insn, regs);
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break;
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case ISA_CMPEQ: /* cmpeq Rsrc1, Rsrc2 */
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res = emu_cmpeq(insn, regs);
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break;
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case ISA_CMPU: /* cmpu Rsrc1, Rsrc2 */
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res = emu_cmpu(insn, regs);
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break;
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case ISA_CMPZ: /* cmpz Rsrc */
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res = emu_cmpz(insn, regs);
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break;
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case ISA_MV: /* mv Rdest, Rsrc */
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res = emu_mv(insn, regs);
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break;
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case ISA_NEG: /* neg Rdest, Rsrc */
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res = emu_neg(insn, regs);
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break;
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case ISA_NOT: /* not Rdest, Rsrc */
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res = emu_not(insn, regs);
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break;
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case ISA_OR: /* or Rdest, Rsrc */
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res = emu_or(insn, regs);
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break;
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case ISA_SUB: /* sub Rdest, Rsrc */
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res = emu_sub(insn, regs);
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break;
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case ISA_SUBX: /* subx Rdest, Rsrc */
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res = emu_subx(insn, regs);
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break;
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case ISA_XOR: /* xor Rdest, Rsrc */
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res = emu_xor(insn, regs);
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break;
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case ISA_MUL: /* mul Rdest, Rsrc */
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res = emu_mul(insn, regs);
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break;
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case ISA_MULLO_A0: /* mullo Rsrc1, Rsrc2 */
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res = emu_mullo_a0(insn, regs);
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break;
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case ISA_MULLO_A1: /* mullo Rsrc1, Rsrc2 */
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res = emu_mullo_a1(insn, regs);
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break;
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default:
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break;
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}
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if (!res)
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return 0;
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switch(insn & 0x70ff) {
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case ISA_MVFACMI_A0: /* mvfacmi Rdest */
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res = emu_mvfacmi_a0(insn, regs);
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break;
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case ISA_MVFACMI_A1: /* mvfacmi Rdest */
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res = emu_mvfacmi_a1(insn, regs);
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break;
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default:
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break;
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}
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return res;
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}
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#endif /* CONFIG_ISA_DUAL_ISSUE */
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/*
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* ld : ?010 dest 1100 src
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* 0010 dest 1110 src : ld Rdest, @Rsrc+
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* ldh : ?010 dest 1010 src
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* lduh : ?010 dest 1011 src
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* st : ?010 src1 0100 src2
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* 0010 src1 0110 src2 : st Rsrc1, @+Rsrc2
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* 0010 src1 0111 src2 : st Rsrc1, @-Rsrc2
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* sth : ?010 src1 0010 src2
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*/
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static int insn_check(unsigned long insn, struct pt_regs *regs,
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unsigned char **ucp)
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{
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int res = 0;
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/*
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* 32bit insn
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* ld Rdest, @(disp16, Rsrc)
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* st Rdest, @(disp16, Rsrc)
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*/
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if (insn & 0x80000000) { /* 32bit insn */
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*ucp += (short)(insn & 0x0000ffff);
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regs->bpc += 4;
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} else { /* 16bit insn */
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#ifdef CONFIG_ISA_DUAL_ISSUE
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/* parallel exec check */
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if (!(regs->bpc & 0x2) && insn & 0x8000) {
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res = emu_m32r2((unsigned short)insn, regs);
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regs->bpc += 4;
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} else
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#endif /* CONFIG_ISA_DUAL_ISSUE */
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regs->bpc += 2;
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}
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return res;
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}
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static int emu_ld(unsigned long insn32, struct pt_regs *regs)
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{
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unsigned char *ucp;
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unsigned long val;
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unsigned short insn16;
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int size, src;
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insn16 = insn32 >> 16;
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src = REG2(insn16);
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ucp = (unsigned char *)get_reg(regs, src);
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if (insn_check(insn32, regs, &ucp))
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return -1;
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size = insn16 & 0x0040 ? 4 : 2;
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if (copy_from_user(&val, ucp, size))
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return -1;
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if (size == 2)
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val >>= 16;
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/* ldh sign check */
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if ((insn16 & 0x00f0) == 0x00a0 && (val & 0x8000))
|
|
val |= 0xffff0000;
|
|
|
|
set_reg(regs, REG1(insn16), val);
|
|
|
|
/* ld increment check */
|
|
if ((insn16 & 0xf0f0) == ISA_LD2) /* ld Rdest, @Rsrc+ */
|
|
set_reg(regs, src, (unsigned long)(ucp + 4));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int emu_st(unsigned long insn32, struct pt_regs *regs)
|
|
{
|
|
unsigned char *ucp;
|
|
unsigned long val;
|
|
unsigned short insn16;
|
|
int size, src2;
|
|
|
|
insn16 = insn32 >> 16;
|
|
src2 = REG2(insn16);
|
|
|
|
ucp = (unsigned char *)get_reg(regs, src2);
|
|
|
|
if (insn_check(insn32, regs, &ucp))
|
|
return -1;
|
|
|
|
size = insn16 & 0x0040 ? 4 : 2;
|
|
val = get_reg(regs, REG1(insn16));
|
|
if (size == 2)
|
|
val <<= 16;
|
|
|
|
/* st inc/dec check */
|
|
if ((insn16 & 0xf0e0) == 0x2060) {
|
|
if (insn16 & 0x0010)
|
|
ucp -= 4;
|
|
else
|
|
ucp += 4;
|
|
|
|
set_reg(regs, src2, (unsigned long)ucp);
|
|
}
|
|
|
|
if (copy_to_user(ucp, &val, size))
|
|
return -1;
|
|
|
|
/* sth inc check */
|
|
if ((insn16 & 0xf0f0) == ISA_STH2) {
|
|
ucp += 2;
|
|
set_reg(regs, src2, (unsigned long)ucp);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int handle_unaligned_access(unsigned long insn32, struct pt_regs *regs)
|
|
{
|
|
unsigned short insn16;
|
|
int res;
|
|
|
|
insn16 = insn32 >> 16;
|
|
|
|
/* ld or st check */
|
|
if ((insn16 & 0x7000) != 0x2000)
|
|
return -1;
|
|
|
|
/* insn alignment check */
|
|
if ((insn16 & 0x8000) && (regs->bpc & 3))
|
|
return -1;
|
|
|
|
if (insn16 & 0x0080) /* ld */
|
|
res = emu_ld(insn32, regs);
|
|
else /* st */
|
|
res = emu_st(insn32, regs);
|
|
|
|
return res;
|
|
}
|
|
|