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1ee9530a71
Patch from Lothar Wassmann The patch makes sure, that the ouptut functions of pins are restored before restoring the Alternat Function settings, preventing pins from being intermediately configured for undefined or unwanted alternate functions. Here is the original comment: I've got a PXA270 system that uses GPIO80 as nCS4. This system did hang on resume. Digging into the problem I found that the processor stalled immediately when restoring the GAFR2_U register which restored the alternate function for GPIO80. Since the GPDR registers were restored after the GAFR registers, the offending GPIO was configured as input at this point. Thus the alternate function that was in effect after restoring the GAFR was in fact the input function "MBREQ" instead of the output function "nCS4". The "PXA27x Processor Family Developer's Manual" (Footnote in Table 6-1 on page 6-3) states that: "The MBREQ alternate function must not be enabled until the PSSR[RDH] bit field is cleared. For more details, see Table 3-15, "PSSR Bit Definitions" on page 3-71." There is another note in the Developer's Manual (chapter 24.4.2 "GPIO operation as Alternate Function" on page 24-4) stating that: "Configuring a GPIO for an alternate function that is not defined for it causes unpredictable results." Since some GPIOs have no input function defined, and to prevent inadvertedly programming the MBREQ function on some pin, the GAFR registers should be restored after the GPDR registers have been restored. Additional provisions have to be made when the MBREQ function is actually required. The corresponding GAFR bits should not be restored with the regular GAFR restore, but must be set only after the PSSR bits have been cleared. Signed-off-by: Lothar Wassmann <LW@KARO-electronics.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
243 lines
5.5 KiB
C
243 lines
5.5 KiB
C
/*
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* PXA250/210 Power Management Routines
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*
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* Original code for the SA11x0:
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* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
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*
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* Modified for the PXA250 by Nicolas Pitre:
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* Copyright (c) 2002 Monta Vista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/time.h>
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#include <asm/hardware.h>
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#include <asm/memory.h>
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#include <asm/system.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/lubbock.h>
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#include <asm/mach/time.h>
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/*
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* Debug macros
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*/
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#undef DEBUG
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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#define RESTORE_GPLEVEL(n) do { \
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GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
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GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
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} while (0)
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum { SLEEP_SAVE_START = 0,
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SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
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SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
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SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
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SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
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SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
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SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
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SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
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SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
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SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_ICMR,
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SLEEP_SAVE_CKEN,
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#ifdef CONFIG_PXA27x
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SLEEP_SAVE_MDREFR,
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SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
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SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
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#endif
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SLEEP_SAVE_CKSUM,
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SLEEP_SAVE_SIZE
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};
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int pxa_pm_enter(suspend_state_t state)
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{
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unsigned long sleep_save[SLEEP_SAVE_SIZE];
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unsigned long checksum = 0;
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struct timespec delta, rtc;
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int i;
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extern void pxa_cpu_pm_enter(suspend_state_t state);
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#ifdef CONFIG_IWMMXT
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/* force any iWMMXt context to ram **/
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iwmmxt_task_disable(NULL);
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#endif
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/* preserve current time */
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rtc.tv_sec = RCNR;
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rtc.tv_nsec = 0;
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save_time_delta(&delta, &rtc);
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SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
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SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
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SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
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SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
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SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
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SAVE(GAFR0_L); SAVE(GAFR0_U);
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SAVE(GAFR1_L); SAVE(GAFR1_U);
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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#ifdef CONFIG_PXA27x
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SAVE(MDREFR);
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SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
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SAVE(GAFR3_L); SAVE(GAFR3_U);
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SAVE(PWER); SAVE(PCFR); SAVE(PRER);
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SAVE(PFER); SAVE(PKWR);
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#endif
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SAVE(ICMR);
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ICMR = 0;
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SAVE(CKEN);
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SAVE(PSTR);
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/* Note: wake up source are set up in each machine specific files */
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/* clear GPIO transition detect bits */
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GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
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#ifdef CONFIG_PXA27x
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GEDR3 = GEDR3;
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#endif
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/* Clear sleep reset status */
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RCSR = RCSR_SMR;
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/* before sleeping, calculate and save a checksum */
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for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
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checksum += sleep_save[i];
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sleep_save[SLEEP_SAVE_CKSUM] = checksum;
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/* *** go zzz *** */
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pxa_cpu_pm_enter(state);
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cpu_init();
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/* after sleeping, validate the checksum */
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checksum = 0;
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for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
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checksum += sleep_save[i];
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/* if invalid, display message and wait for a hardware reset */
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if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
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#ifdef CONFIG_ARCH_LUBBOCK
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LUB_HEXLED = 0xbadbadc5;
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#endif
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while (1)
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pxa_cpu_pm_enter(state);
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}
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/* ensure not to come back here if it wasn't intended */
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PSPR = 0;
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/* restore registers */
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RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
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RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
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RESTORE(GAFR0_L); RESTORE(GAFR0_U);
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RESTORE(GAFR1_L); RESTORE(GAFR1_U);
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RESTORE(GAFR2_L); RESTORE(GAFR2_U);
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RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
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RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
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RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
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#ifdef CONFIG_PXA27x
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RESTORE(MDREFR);
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RESTORE_GPLEVEL(3); RESTORE(GPDR3);
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RESTORE(GAFR3_L); RESTORE(GAFR3_U);
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RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
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RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
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RESTORE(PFER); RESTORE(PKWR);
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#endif
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PSSR = PSSR_RDH | PSSR_PH;
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RESTORE(CKEN);
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ICLR = 0;
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ICCR = 1;
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RESTORE(ICMR);
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RESTORE(PSTR);
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/* restore current time */
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rtc.tv_sec = RCNR;
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restore_time_delta(&delta, &rtc);
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#ifdef DEBUG
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printk(KERN_DEBUG "*** made it back from resume\n");
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#endif
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return 0;
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}
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EXPORT_SYMBOL_GPL(pxa_pm_enter);
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unsigned long sleep_phys_sp(void *sp)
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{
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return virt_to_phys(sp);
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}
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/*
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* Called after processes are frozen, but before we shut down devices.
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*/
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int pxa_pm_prepare(suspend_state_t state)
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{
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extern int pxa_cpu_pm_prepare(suspend_state_t state);
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return pxa_cpu_pm_prepare(state);
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}
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EXPORT_SYMBOL_GPL(pxa_pm_prepare);
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/*
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* Called after devices are re-setup, but before processes are thawed.
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*/
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int pxa_pm_finish(suspend_state_t state)
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{
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return 0;
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}
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EXPORT_SYMBOL_GPL(pxa_pm_finish);
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/*
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* Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
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*/
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static struct pm_ops pxa_pm_ops = {
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.pm_disk_mode = PM_DISK_FIRMWARE,
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.prepare = pxa_pm_prepare,
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.enter = pxa_pm_enter,
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.finish = pxa_pm_finish,
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};
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static int __init pxa_pm_init(void)
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{
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pm_set_ops(&pxa_pm_ops);
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return 0;
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}
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device_initcall(pxa_pm_init);
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