mirror of
https://github.com/edk2-porting/linux-next.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
249 lines
7.1 KiB
C
249 lines
7.1 KiB
C
/*
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* Apple Peripheral System Controller (PSC)
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*
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* The PSC is used on the AV Macs to control IO functions not handled
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* by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
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* channels.
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*
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* The first seven DMA channels appear to be "one-shot" and are actually
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* sets of two channels; one member is active while the other is being
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* configured, and then you flip the active member and start all over again.
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* The one-shot channels are grouped together and are:
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*
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* 1. SCSI
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* 2. Ethernet Read
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* 3. Ethernet Write
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* 4. Floppy Disk Controller
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* 5. SCC Channel A Receive
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* 6. SCC Channel B Receive
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* 7. SCC Channel A Transmit
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*
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* The remaining two channels are handled somewhat differently. They appear
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* to be closely tied and share one set of registers. They also seem to run
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* continuously, although how you keep the buffer filled in this scenario is
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* not understood as there seems to be only one input and one output buffer
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* pointer.
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*
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* Much of this was extrapolated from what was known about the Ethernet
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* registers and subsequently confirmed using MacsBug (ie by pinging the
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* machine with easy-to-find patterns and looking for them in the DMA
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* buffers, or by sending a file over the serial ports and finding the
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* file in the buffers.)
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*
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* 1999-05-25 (jmt)
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*/
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#define PSC_BASE (0x50F31000)
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/*
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* The IER/IFR registers work like the VIA, except that it has 4
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* of them each on different interrupt levels, and each register
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* set only seems to handle four interrupts instead of seven.
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*
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* To access a particular set of registers, add 0xn0 to the base
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* where n = 3,4,5 or 6.
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*/
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#define pIFRbase 0x100
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#define pIERbase 0x104
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/*
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* One-shot DMA control registers
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*/
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#define PSC_MYSTERY 0x804
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#define PSC_CTL_BASE 0xC00
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#define PSC_SCSI_CTL 0xC00
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#define PSC_ENETRD_CTL 0xC10
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#define PSC_ENETWR_CTL 0xC20
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#define PSC_FDC_CTL 0xC30
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#define PSC_SCCA_CTL 0xC40
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#define PSC_SCCB_CTL 0xC50
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#define PSC_SCCATX_CTL 0xC60
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/*
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* DMA channels. Add +0x10 for the second channel in the set.
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* You're supposed to use one channel while the other runs and
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* then flip channels and do the whole thing again.
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*/
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#define PSC_ADDR_BASE 0x1000
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#define PSC_LEN_BASE 0x1004
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#define PSC_CMD_BASE 0x1008
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#define PSC_SET0 0x00
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#define PSC_SET1 0x10
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#define PSC_SCSI_ADDR 0x1000 /* confirmed */
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#define PSC_SCSI_LEN 0x1004 /* confirmed */
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#define PSC_SCSI_CMD 0x1008 /* confirmed */
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#define PSC_ENETRD_ADDR 0x1020 /* confirmed */
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#define PSC_ENETRD_LEN 0x1024 /* confirmed */
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#define PSC_ENETRD_CMD 0x1028 /* confirmed */
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#define PSC_ENETWR_ADDR 0x1040 /* confirmed */
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#define PSC_ENETWR_LEN 0x1044 /* confirmed */
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#define PSC_ENETWR_CMD 0x1048 /* confirmed */
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#define PSC_FDC_ADDR 0x1060 /* strongly suspected */
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#define PSC_FDC_LEN 0x1064 /* strongly suspected */
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#define PSC_FDC_CMD 0x1068 /* strongly suspected */
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#define PSC_SCCA_ADDR 0x1080 /* confirmed */
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#define PSC_SCCA_LEN 0x1084 /* confirmed */
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#define PSC_SCCA_CMD 0x1088 /* confirmed */
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#define PSC_SCCB_ADDR 0x10A0 /* confirmed */
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#define PSC_SCCB_LEN 0x10A4 /* confirmed */
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#define PSC_SCCB_CMD 0x10A8 /* confirmed */
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#define PSC_SCCATX_ADDR 0x10C0 /* confirmed */
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#define PSC_SCCATX_LEN 0x10C4 /* confirmed */
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#define PSC_SCCATX_CMD 0x10C8 /* confirmed */
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/*
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* Free-running DMA registers. The only part known for sure are the bits in
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* the control register, the buffer addresses and the buffer length. Everything
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* else is anybody's guess.
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*
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* These registers seem to be mirrored every thirty-two bytes up until offset
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* 0x300. It's safe to assume then that a new set of registers starts there.
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*/
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#define PSC_SND_CTL 0x200 /*
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* [ 16-bit ]
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* Sound (Singer?) control register.
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*
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* bit 0 : ????
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* bit 1 : ????
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* bit 2 : Set to one to enable sound
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* output. Possibly a mute flag.
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* bit 3 : ????
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* bit 4 : ????
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* bit 5 : ????
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* bit 6 : Set to one to enable pass-thru
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* audio. In this mode the audio data
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* seems to appear in both the input
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* buffer and the output buffer.
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* bit 7 : Set to one to activate the
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* sound input DMA or zero to
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* disable it.
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* bit 8 : Set to one to activate the
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* sound output DMA or zero to
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* disable it.
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* bit 9 : \
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* bit 11 : |
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* These two bits control the sample
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* rate. Usually set to binary 10 and
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* MacOS 8.0 says I'm at 48 KHz. Using
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* a binary value of 01 makes things
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* sound about 1/2 speed (24 KHz?) and
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* binary 00 is slower still (22 KHz?)
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*
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* Setting this to 0x0000 is a good way to
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* kill all DMA at boot time so that the
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* PSC won't overwrite the kernel image
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* with sound data.
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*/
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/*
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* 0x0202 - 0x0203 is unused. Writing there
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* seems to clobber the control register.
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*/
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#define PSC_SND_SOURCE 0x204 /*
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* [ 32-bit ]
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* Controls input source and volume:
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*
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* bits 12-15 : input source volume, 0 - F
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* bits 16-19 : unknown, always 0x5
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* bits 20-23 : input source selection:
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* 0x3 = CD Audio
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* 0x4 = External Audio
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*
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* The volume is definitely not the general
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* output volume as it doesn't affect the
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* alert sound volume.
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*/
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#define PSC_SND_STATUS1 0x208 /*
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* [ 32-bit ]
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* Appears to be a read-only status register.
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* The usual value is 0x00400002.
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*/
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#define PSC_SND_HUH3 0x20C /*
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* [ 16-bit ]
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* Unknown 16-bit value, always 0x0000.
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*/
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#define PSC_SND_BITS2GO 0x20E /*
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* [ 16-bit ]
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* Counts down to zero from some constant
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* value. The value appears to be the
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* number of _bits_ remaining before the
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* buffer is full, which would make sense
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* since Apple's docs say the sound DMA
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* channels are 1 bit wide.
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*/
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#define PSC_SND_INADDR 0x210 /*
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* [ 32-bit ]
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* Address of the sound input DMA buffer
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*/
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#define PSC_SND_OUTADDR 0x214 /*
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* [ 32-bit ]
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* Address of the sound output DMA buffer
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*/
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#define PSC_SND_LEN 0x218 /*
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* [ 16-bit ]
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* Length of both buffers in eight-byte units.
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*/
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#define PSC_SND_HUH4 0x21A /*
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* [ 16-bit ]
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* Unknown, always 0x0000.
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*/
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#define PSC_SND_STATUS2 0x21C /*
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* [ 16-bit ]
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* Appears to e a read-only status register.
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* The usual value is 0x0200.
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*/
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#define PSC_SND_HUH5 0x21E /*
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* [ 16-bit ]
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* Unknown, always 0x0000.
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*/
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#ifndef __ASSEMBLY__
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extern volatile __u8 *psc;
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extern int psc_present;
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/*
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* Access functions
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*/
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static inline void psc_write_byte(int offset, __u8 data)
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{
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*((volatile __u8 *)(psc + offset)) = data;
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}
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static inline void psc_write_word(int offset, __u16 data)
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{
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*((volatile __u16 *)(psc + offset)) = data;
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}
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static inline void psc_write_long(int offset, __u32 data)
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{
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*((volatile __u32 *)(psc + offset)) = data;
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}
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static inline u8 psc_read_byte(int offset)
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{
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return *((volatile __u8 *)(psc + offset));
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}
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static inline u16 psc_read_word(int offset)
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{
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return *((volatile __u16 *)(psc + offset));
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}
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static inline u32 psc_read_long(int offset)
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{
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return *((volatile __u32 *)(psc + offset));
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}
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#endif /* __ASSEMBLY__ */
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