mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-17 09:43:59 +08:00
c44166fe5f
Changeset58ad30cf91("docs: fix reference to core-api/namespaces.rst") enabled a new feature at Sphinx: it will now generate index for each document title, plus to each chapter inside it. There's a drawback, though: one document cannot have two sections with the same name anymore. A followup patch will change the logic of autosectionlabel to avoid most creating references for every single section title, but still we need to be able to reference the chapters inside a document. There are a few places where there are two chapters with the same name. This patch renames one of the chapters, in order to avoid symbol conflict within the same document. PS.: as I don't speach Chinese, I had some help from a friend (Wen Liu) at the Chinese translation for "publishing patches" for this document: Documentation/translations/zh_CN/process/5.Posting.rst Fixes:58ad30cf91("docs: fix reference to core-api/namespaces.rst") Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/2bffb91e4a63d41bf5fae1c23e1e8b3bba0b8806.1584716446.git.mchehab+huawei@kernel.org Signed-off-by: Jonathan Corbet <corbet@lwn.net>
116 lines
3.9 KiB
ReStructuredText
116 lines
3.9 KiB
ReStructuredText
===================
|
|
Linux IOMMU Support
|
|
===================
|
|
|
|
The architecture spec can be obtained from the below location.
|
|
|
|
http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
|
|
|
|
This guide gives a quick cheat sheet for some basic understanding.
|
|
|
|
Some Keywords
|
|
|
|
- DMAR - DMA remapping
|
|
- DRHD - DMA Remapping Hardware Unit Definition
|
|
- RMRR - Reserved memory Region Reporting Structure
|
|
- ZLR - Zero length reads from PCI devices
|
|
- IOVA - IO Virtual address.
|
|
|
|
Basic stuff
|
|
-----------
|
|
|
|
ACPI enumerates and lists the different DMA engines in the platform, and
|
|
device scope relationships between PCI devices and which DMA engine controls
|
|
them.
|
|
|
|
What is RMRR?
|
|
-------------
|
|
|
|
There are some devices the BIOS controls, for e.g USB devices to perform
|
|
PS2 emulation. The regions of memory used for these devices are marked
|
|
reserved in the e820 map. When we turn on DMA translation, DMA to those
|
|
regions will fail. Hence BIOS uses RMRR to specify these regions along with
|
|
devices that need to access these regions. OS is expected to setup
|
|
unity mappings for these regions for these devices to access these regions.
|
|
|
|
How is IOVA generated?
|
|
----------------------
|
|
|
|
Well behaved drivers call pci_map_*() calls before sending command to device
|
|
that needs to perform DMA. Once DMA is completed and mapping is no longer
|
|
required, device performs a pci_unmap_*() calls to unmap the region.
|
|
|
|
The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
|
|
device has its own domain (hence protection). Devices under p2p bridges
|
|
share the virtual address with all devices under the p2p bridge due to
|
|
transaction id aliasing for p2p bridges.
|
|
|
|
IOVA generation is pretty generic. We used the same technique as vmalloc()
|
|
but these are not global address spaces, but separate for each domain.
|
|
Different DMA engines may support different number of domains.
|
|
|
|
We also allocate guard pages with each mapping, so we can attempt to catch
|
|
any overflow that might happen.
|
|
|
|
|
|
Graphics Problems?
|
|
------------------
|
|
If you encounter issues with graphics devices, you can try adding
|
|
option intel_iommu=igfx_off to turn off the integrated graphics engine.
|
|
If this fixes anything, please ensure you file a bug reporting the problem.
|
|
|
|
Some exceptions to IOVA
|
|
-----------------------
|
|
Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
|
|
The same is true for peer to peer transactions. Hence we reserve the
|
|
address from PCI MMIO ranges so they are not allocated for IOVA addresses.
|
|
|
|
|
|
Fault reporting
|
|
---------------
|
|
When errors are reported, the DMA engine signals via an interrupt. The fault
|
|
reason and device that caused it with fault reason is printed on console.
|
|
|
|
See below for sample.
|
|
|
|
|
|
Boot Message Sample
|
|
-------------------
|
|
|
|
Something like this gets printed indicating presence of DMAR tables
|
|
in ACPI.
|
|
|
|
ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
|
|
|
|
When DMAR is being processed and initialized by ACPI, prints DMAR locations
|
|
and any RMRR's processed::
|
|
|
|
ACPI DMAR:Host address width 36
|
|
ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
|
|
ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
|
|
ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
|
|
ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
|
|
ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
|
|
|
|
When DMAR is enabled for use, you will notice..
|
|
|
|
PCI-DMA: Using DMAR IOMMU
|
|
-------------------------
|
|
|
|
Fault reporting
|
|
^^^^^^^^^^^^^^^
|
|
|
|
::
|
|
|
|
DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
|
|
DMAR:[fault reason 05] PTE Write access is not set
|
|
DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
|
|
DMAR:[fault reason 05] PTE Write access is not set
|
|
|
|
TBD
|
|
----
|
|
|
|
- For compatibility testing, could use unity map domain for all devices, just
|
|
provide a 1-1 for all useful memory under a single domain for all devices.
|
|
- API for paravirt ops for abstracting functionality for VMM folks.
|