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https://github.com/edk2-porting/linux-next.git
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bb19a7513d
This patch adds the interrupt definitions for EXYNOS5250 at <mach/irqs.h> file and it is needed for EXYNOS5250 SoC. As a note, for single zImage of EXYNOS4 and EXYNOS5, prefix of EXYNOS4_ and EXYNOS5_ has been added. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
/* arch/arm/plat-samsung/irq-vic-timer.c
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* originally part of arch/arm/plat-s3c64xx/irq.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Interrupt handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/cpu.h>
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#include <plat/irq-vic-timer.h>
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#include <plat/regs-timer.h>
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#include <asm/mach/irq.h>
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static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_get_chip(irq);
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chained_irq_enter(chip, desc);
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generic_handle_irq((int)desc->irq_data.handler_data);
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chained_irq_exit(chip, desc);
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}
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/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
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static void s3c_irq_timer_ack(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = (1 << 5) << (d->irq - gc->irq_base);
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irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
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}
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/**
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* s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
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* @num: Number of timers to initialize
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* @timer_irq: Base IRQ number to be used for the timers.
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*
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* Register the necessary IRQ chaining and support for the timer IRQs
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* chained of the VIC.
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*/
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void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
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{
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unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
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IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
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struct irq_chip_generic *s3c_tgc;
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struct irq_chip_type *ct;
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unsigned int i;
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#ifdef CONFIG_ARCH_EXYNOS
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if (soc_is_exynos5250()) {
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pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
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pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
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pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
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pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
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pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
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} else {
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pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
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pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
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pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
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pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
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pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
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}
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#endif
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s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
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S3C64XX_TINT_CSTAT, handle_level_irq);
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if (!s3c_tgc) {
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pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n",
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__func__, timer_irq);
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return;
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}
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ct = s3c_tgc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_ack = s3c_irq_timer_ack;
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irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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/* Clear the upper bits of the mask_cache*/
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s3c_tgc->mask_cache &= 0x1f;
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for (i = 0; i < num; i++, timer_irq++) {
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irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
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irq_set_handler_data(pirq[i], (void *)timer_irq);
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}
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}
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