Andrew Waterman 08f051eda3 RISC-V: Flush I$ when making a dirty page executable ... The RISC-V ISA allows for instruction caches that are not coherent WRT stores, even on a single hart. As a result, we need to explicitly flush the instruction cache whenever marking a dirty page as executable in order to preserve the correct system behavior. Local instruction caches aren't that scary (our implementations actually flush the cache, but RISC-V is defined to allow higher-performance implementations to exist), but RISC-V defines no way to perform an instruction cache shootdown. When explicitly asked to do so we can shoot down remote instruction caches via an IPI, but this is a bit on the slow side. Instead of requiring an IPI to all harts whenever marking a page as executable, we simply flush the currently running harts. In order to maintain correct behavior, we additionally mark every other hart as needing a deferred instruction cache which will be taken before anything runs on it. Signed-off-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2017-11-30 12:58:25 -08:00
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cacheflush.c	RISC-V: Flush I$ when making a dirty page executable	2017-11-30 12:58:25 -08:00
extable.c	RISC-V: ELF and module implementation	2017-09-26 15:26:46 -07:00
fault.c	RISC-V: Paging and MMU	2017-09-26 15:26:47 -07:00
init.c
ioremap.c	RISC-V: Device, timer, IRQs, and the SBI	2017-09-26 15:26:47 -07:00
Makefile	RISC-V: Flush I$ when making a dirty page executable	2017-11-30 12:58:25 -08:00