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https://github.com/edk2-porting/linux-next.git
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7356f0b26b
In 3630, DPLL4M2 output can be 96MHz or 192MHz (for SGX to run at 192). This patch has changes to support this feature. 96MHz clock is generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register. SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's functional clock. In summary changes done are: 1. Added a feature called omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive its clock from omap_192m_alwon_ck Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: fixed whitespace] Signed-off-by: Paul Walmsley <paul@pwsan.com>
426 lines
10 KiB
C
426 lines
10 KiB
C
/*
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* linux/arch/arm/mach-omap2/id.c
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*
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* OMAP2 CPU identification code
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*
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* Copyright (C) 2005 Nokia Corporation
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* Written by Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/cputype.h>
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#include <plat/common.h>
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#include <plat/control.h>
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#include <plat/cpu.h>
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static struct omap_chip_id omap_chip;
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static unsigned int omap_revision;
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u32 omap3_features;
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unsigned int omap_rev(void)
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{
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return omap_revision;
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}
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EXPORT_SYMBOL(omap_rev);
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/**
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* omap_chip_is - test whether currently running OMAP matches a chip type
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* @oc: omap_chip_t to test against
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*
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* Test whether the currently-running OMAP chip matches the supplied
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* chip type 'oc'. Returns 1 upon a match; 0 upon failure.
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*/
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int omap_chip_is(struct omap_chip_id oci)
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{
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return (oci.oc & omap_chip.oc) ? 1 : 0;
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}
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EXPORT_SYMBOL(omap_chip_is);
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int omap_type(void)
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{
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u32 val = 0;
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if (cpu_is_omap24xx()) {
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val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
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} else if (cpu_is_omap34xx()) {
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val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
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} else {
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pr_err("Cannot detect omap type!\n");
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goto out;
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}
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val &= OMAP2_DEVICETYPE_MASK;
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val >>= 8;
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out:
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return val;
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}
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EXPORT_SYMBOL(omap_type);
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/*----------------------------------------------------------------------------*/
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#define OMAP_TAP_IDCODE 0x0204
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#define OMAP_TAP_DIE_ID_0 0x0218
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#define OMAP_TAP_DIE_ID_1 0x021C
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#define OMAP_TAP_DIE_ID_2 0x0220
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#define OMAP_TAP_DIE_ID_3 0x0224
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#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
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struct omap_id {
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u16 hawkeye; /* Silicon type (Hawkeye id) */
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u8 dev; /* Device type from production_id reg */
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u32 type; /* Combined type id copied to omap_revision */
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};
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/* Register values to detect the OMAP version */
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static struct omap_id omap_ids[] __initdata = {
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{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
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{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
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{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
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{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
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{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
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{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
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};
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static void __iomem *tap_base;
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static u16 tap_prod_id;
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void __init omap24xx_check_revision(void)
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{
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int i, j;
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u32 idcode, prod_id;
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u16 hawkeye;
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u8 dev_type, rev;
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idcode = read_tap_reg(OMAP_TAP_IDCODE);
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prod_id = read_tap_reg(tap_prod_id);
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hawkeye = (idcode >> 12) & 0xffff;
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rev = (idcode >> 28) & 0x0f;
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dev_type = (prod_id >> 16) & 0x0f;
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pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
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idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
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pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
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read_tap_reg(OMAP_TAP_DIE_ID_0));
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pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
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read_tap_reg(OMAP_TAP_DIE_ID_1),
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(read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
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pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
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read_tap_reg(OMAP_TAP_DIE_ID_2));
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pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
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read_tap_reg(OMAP_TAP_DIE_ID_3));
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pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
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prod_id, dev_type);
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/* Check hawkeye ids */
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for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
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if (hawkeye == omap_ids[i].hawkeye)
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break;
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}
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if (i == ARRAY_SIZE(omap_ids)) {
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printk(KERN_ERR "Unknown OMAP CPU id\n");
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return;
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}
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for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
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if (dev_type == omap_ids[j].dev)
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break;
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}
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if (j == ARRAY_SIZE(omap_ids)) {
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printk(KERN_ERR "Unknown OMAP device type. "
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"Handling it as OMAP%04x\n",
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omap_ids[i].type >> 16);
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j = i;
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}
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pr_info("OMAP%04x", omap_rev() >> 16);
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if ((omap_rev() >> 8) & 0x0f)
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pr_info("ES%x", (omap_rev() >> 12) & 0xf);
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pr_info("\n");
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}
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#define OMAP3_CHECK_FEATURE(status,feat) \
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if (((status & OMAP3_ ##feat## _MASK) \
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>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
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omap3_features |= OMAP3_HAS_ ##feat; \
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}
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void __init omap3_check_features(void)
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{
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u32 status;
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omap3_features = 0;
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status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
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OMAP3_CHECK_FEATURE(status, L2CACHE);
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OMAP3_CHECK_FEATURE(status, IVA);
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OMAP3_CHECK_FEATURE(status, SGX);
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OMAP3_CHECK_FEATURE(status, NEON);
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OMAP3_CHECK_FEATURE(status, ISP);
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if (cpu_is_omap3630())
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omap3_features |= OMAP3_HAS_192MHZ_CLK;
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/*
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* TODO: Get additional info (where applicable)
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* e.g. Size of L2 cache.
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*/
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}
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void __init omap3_check_revision(void)
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{
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u32 cpuid, idcode;
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u16 hawkeye;
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u8 rev;
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omap_chip.oc = CHIP_IS_OMAP3430;
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/*
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* We cannot access revision registers on ES1.0.
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* If the processor type is Cortex-A8 and the revision is 0x0
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* it means its Cortex r0p0 which is 3430 ES1.0.
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*/
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cpuid = read_cpuid(CPUID_ID);
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if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
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omap_revision = OMAP3430_REV_ES1_0;
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omap_chip.oc |= CHIP_IS_OMAP3430ES1;
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return;
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}
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/*
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* Detection for 34xx ES2.0 and above can be done with just
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* hawkeye and rev. See TRM 1.5.2 Device Identification.
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* Note that rev does not map directly to our defined processor
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* revision numbers as ES1.0 uses value 0.
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*/
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idcode = read_tap_reg(OMAP_TAP_IDCODE);
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hawkeye = (idcode >> 12) & 0xffff;
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rev = (idcode >> 28) & 0xff;
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switch (hawkeye) {
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case 0xb7ae:
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/* Handle 34xx/35xx devices */
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switch (rev) {
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case 0: /* Take care of early samples */
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case 1:
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omap_revision = OMAP3430_REV_ES2_0;
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omap_chip.oc |= CHIP_IS_OMAP3430ES2;
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break;
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case 2:
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omap_revision = OMAP3430_REV_ES2_1;
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omap_chip.oc |= CHIP_IS_OMAP3430ES2;
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break;
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case 3:
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omap_revision = OMAP3430_REV_ES3_0;
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omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
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break;
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case 4:
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omap_revision = OMAP3430_REV_ES3_1;
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omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
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break;
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case 7:
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/* FALLTHROUGH */
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default:
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/* Use the latest known revision as default */
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omap_revision = OMAP3430_REV_ES3_1_2;
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/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
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omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
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}
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break;
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case 0xb868:
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/* Handle OMAP35xx/AM35xx devices
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*
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* Set the device to be OMAP3505 here. Actual device
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* is identified later based on the features.
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*
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* REVISIT: AM3505/AM3517 should have their own CHIP_IS
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*/
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omap_revision = OMAP3505_REV(rev);
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omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
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break;
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case 0xb891:
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/* FALLTHROUGH */
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default:
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/* Unknown default to latest silicon rev as default*/
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omap_revision = OMAP3630_REV_ES1_0;
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omap_chip.oc |= CHIP_IS_OMAP3630ES1;
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}
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}
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void __init omap4_check_revision(void)
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{
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u32 idcode;
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u16 hawkeye;
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u8 rev;
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char *rev_name = "ES1.0";
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/*
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* The IC rev detection is done with hawkeye and rev.
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* Note that rev does not map directly to defined processor
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* revision numbers as ES1.0 uses value 0.
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*/
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idcode = read_tap_reg(OMAP_TAP_IDCODE);
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hawkeye = (idcode >> 12) & 0xffff;
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rev = (idcode >> 28) & 0xff;
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if ((hawkeye == 0xb852) && (rev == 0x0)) {
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omap_revision = OMAP4430_REV_ES1_0;
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omap_chip.oc |= CHIP_IS_OMAP4430ES1;
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pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
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return;
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}
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pr_err("Unknown OMAP4 CPU id\n");
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}
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#define OMAP3_SHOW_FEATURE(feat) \
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if (omap3_has_ ##feat()) \
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printk(#feat" ");
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void __init omap3_cpuinfo(void)
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{
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u8 rev = GET_OMAP_REVISION();
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char cpu_name[16], cpu_rev[16];
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/* OMAP3430 and OMAP3530 are assumed to be same.
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*
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* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
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* on available features. Upon detection, update the CPU id
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* and CPU class bits.
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*/
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if (cpu_is_omap3630()) {
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strcpy(cpu_name, "OMAP3630");
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} else if (cpu_is_omap3505()) {
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/*
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* AM35xx devices
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*/
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if (omap3_has_sgx()) {
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omap_revision = OMAP3517_REV(rev);
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strcpy(cpu_name, "AM3517");
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} else {
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/* Already set in omap3_check_revision() */
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strcpy(cpu_name, "AM3505");
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}
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} else if (omap3_has_iva() && omap3_has_sgx()) {
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/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
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strcpy(cpu_name, "OMAP3430/3530");
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} else if (omap3_has_iva()) {
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omap_revision = OMAP3525_REV(rev);
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strcpy(cpu_name, "OMAP3525");
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} else if (omap3_has_sgx()) {
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omap_revision = OMAP3515_REV(rev);
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strcpy(cpu_name, "OMAP3515");
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} else {
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omap_revision = OMAP3503_REV(rev);
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strcpy(cpu_name, "OMAP3503");
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}
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switch (rev) {
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case OMAP_REVBITS_00:
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strcpy(cpu_rev, "1.0");
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break;
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case OMAP_REVBITS_10:
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strcpy(cpu_rev, "2.0");
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break;
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case OMAP_REVBITS_20:
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strcpy(cpu_rev, "2.1");
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break;
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case OMAP_REVBITS_30:
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strcpy(cpu_rev, "3.0");
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break;
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case OMAP_REVBITS_40:
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/* FALLTHROUGH */
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default:
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/* Use the latest known revision as default */
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strcpy(cpu_rev, "3.1");
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}
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/* Print verbose information */
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pr_info("%s ES%s (", cpu_name, cpu_rev);
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OMAP3_SHOW_FEATURE(l2cache);
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OMAP3_SHOW_FEATURE(iva);
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OMAP3_SHOW_FEATURE(sgx);
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OMAP3_SHOW_FEATURE(neon);
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OMAP3_SHOW_FEATURE(isp);
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OMAP3_SHOW_FEATURE(192mhz_clk);
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printk(")\n");
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}
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/*
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* Try to detect the exact revision of the omap we're running on
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*/
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void __init omap2_check_revision(void)
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{
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/*
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* At this point we have an idea about the processor revision set
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* earlier with omap2_set_globals_tap().
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*/
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if (cpu_is_omap24xx()) {
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omap24xx_check_revision();
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} else if (cpu_is_omap34xx()) {
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omap3_check_revision();
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omap3_check_features();
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omap3_cpuinfo();
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return;
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} else if (cpu_is_omap44xx()) {
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omap4_check_revision();
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return;
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} else {
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pr_err("OMAP revision unknown, please fix!\n");
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}
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/*
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* OK, now we know the exact revision. Initialize omap_chip bits
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* for powerdowmain and clockdomain code.
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*/
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if (cpu_is_omap243x()) {
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/* Currently only supports 2430ES2.1 and 2430-all */
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omap_chip.oc |= CHIP_IS_OMAP2430;
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return;
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} else if (cpu_is_omap242x()) {
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/* Currently only supports 2420ES2.1.1 and 2420-all */
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omap_chip.oc |= CHIP_IS_OMAP2420;
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return;
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}
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pr_err("Uninitialized omap_chip, please fix!\n");
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}
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/*
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* Set up things for map_io and processor detection later on. Gets called
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* pretty much first thing from board init. For multi-omap, this gets
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* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
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* detect the exact revision later on in omap2_detect_revision() once map_io
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* is done.
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*/
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void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
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{
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omap_revision = omap2_globals->class;
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tap_base = omap2_globals->tap;
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if (cpu_is_omap34xx())
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tap_prod_id = 0x0210;
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else
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tap_prod_id = 0x0208;
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}
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