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1d22924e1c
The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15 cores (in a 4x4 cluster configuration). The cores within each cluster share an L2 cache, and the clusters are connected to each other via a CCN-504 cache coherent interconnect. This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located above 4GB in the memory map. Signed-off-by: Anders Berg <anders.berg@lsi.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
17 lines
426 B
Plaintext
17 lines
426 B
Plaintext
config ARCH_AXXIA
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bool "LSI Axxia platforms" if (ARCH_MULTI_V7 && ARM_LPAE)
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select ARCH_DMA_ADDR_T_64BIT
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select ARM_AMBA
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select ARM_GIC
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select ARM_TIMER_SP804
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select HAVE_ARM_ARCH_TIMER
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select MFD_SYSCON
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select MIGHT_HAVE_PCI
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select PCI_DOMAINS if PCI
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select ZONE_DMA
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help
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This enables support for the LSI Axxia devices.
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The LSI Axxia platforms require a Flattened Device Tree to be passed
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to the kernel.
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