mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 20:53:53 +08:00
2bedea8f26
This patch removes the bcma_core_pci_power_save() call from
the bcma_core_pci_{up,down}() functions as it tries to schedule
thus requiring to call them from non-atomic context. The function
bcma_core_pci_power_save() is now exported so the calling module
can explicitly use it in non-atomic context. This fixes the
'scheduling while atomic' issue reported by Tod Jackson and
Joe Perches.
[ 13.210710] BUG: scheduling while atomic: dhcpcd/1800/0x00000202
[ 13.210718] Modules linked in: brcmsmac nouveau coretemp kvm_intel kvm cordic brcmutil bcma dell_wmi atl1c ttm mxm_wmi wmi
[ 13.210756] CPU: 2 PID: 1800 Comm: dhcpcd Not tainted 3.11.0-wl #1
[ 13.210762] Hardware name: Alienware M11x R2/M11x R2, BIOS A04 11/23/2010
[ 13.210767] ffff880177c92c40 ffff880170fd1948 ffffffff8169af5b 0000000000000007
[ 13.210777] ffff880170fd1ab0 ffff880170fd1958 ffffffff81697ee2 ffff880170fd19d8
[ 13.210785] ffffffff816a19f5 00000000000f4240 000000000000d080 ffff880170fd1fd8
[ 13.210794] Call Trace:
[ 13.210813] [<ffffffff8169af5b>] dump_stack+0x4f/0x84
[ 13.210826] [<ffffffff81697ee2>] __schedule_bug+0x43/0x51
[ 13.210837] [<ffffffff816a19f5>] __schedule+0x6e5/0x810
[ 13.210845] [<ffffffff816a1c34>] schedule+0x24/0x70
[ 13.210855] [<ffffffff816a04fc>] schedule_hrtimeout_range_clock+0x10c/0x150
[ 13.210867] [<ffffffff810684e0>] ? update_rmtp+0x60/0x60
[ 13.210877] [<ffffffff8106915f>] ? hrtimer_start_range_ns+0xf/0x20
[ 13.210887] [<ffffffff816a054e>] schedule_hrtimeout_range+0xe/0x10
[ 13.210897] [<ffffffff8104f6fb>] usleep_range+0x3b/0x40
[ 13.210910] [<ffffffffa00371af>] bcma_pcie_mdio_set_phy.isra.3+0x4f/0x80 [bcma]
[ 13.210921] [<ffffffffa003729f>] bcma_pcie_mdio_write.isra.4+0xbf/0xd0 [bcma]
[ 13.210932] [<ffffffffa0037498>] bcma_pcie_mdio_writeread.isra.6.constprop.13+0x18/0x30 [bcma]
[ 13.210942] [<ffffffffa00374ee>] bcma_core_pci_power_save+0x3e/0x80 [bcma]
[ 13.210953] [<ffffffffa003765d>] bcma_core_pci_up+0x2d/0x60 [bcma]
[ 13.210975] [<ffffffffa03dc17c>] brcms_c_up+0xfc/0x430 [brcmsmac]
[ 13.210989] [<ffffffffa03d1a7d>] brcms_up+0x1d/0x20 [brcmsmac]
[ 13.211003] [<ffffffffa03d2498>] brcms_ops_start+0x298/0x340 [brcmsmac]
[ 13.211020] [<ffffffff81600a12>] ? cfg80211_netdev_notifier_call+0xd2/0x5f0
[ 13.211030] [<ffffffff815fa53d>] ? packet_notifier+0xad/0x1d0
[ 13.211064] [<ffffffff81656e75>] ieee80211_do_open+0x325/0xf80
[ 13.211076] [<ffffffff8106ac09>] ? __raw_notifier_call_chain+0x9/0x10
[ 13.211086] [<ffffffff81657b41>] ieee80211_open+0x71/0x80
[ 13.211101] [<ffffffff81526267>] __dev_open+0x87/0xe0
[ 13.211109] [<ffffffff8152650c>] __dev_change_flags+0x9c/0x180
[ 13.211117] [<ffffffff815266a3>] dev_change_flags+0x23/0x70
[ 13.211127] [<ffffffff8158cd68>] devinet_ioctl+0x5b8/0x6a0
[ 13.211136] [<ffffffff8158d5c5>] inet_ioctl+0x75/0x90
[ 13.211147] [<ffffffff8150b38b>] sock_do_ioctl+0x2b/0x70
[ 13.211155] [<ffffffff8150b681>] sock_ioctl+0x71/0x2a0
[ 13.211169] [<ffffffff8114ed47>] do_vfs_ioctl+0x87/0x520
[ 13.211180] [<ffffffff8113f159>] ? ____fput+0x9/0x10
[ 13.211198] [<ffffffff8106228c>] ? task_work_run+0x9c/0xd0
[ 13.211202] [<ffffffff8114f271>] SyS_ioctl+0x91/0xb0
[ 13.211208] [<ffffffff816aa252>] system_call_fastpath+0x16/0x1b
[ 13.211217] NOHZ: local_softirq_pending 202
The issue was introduced in v3.11 kernel by following commit:
commit aa51e598d0
Author: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat Aug 24 00:32:31 2013 +0200
brcmsmac: use bcma PCIe up and down functions
replace the calls to bcma_core_pci_extend_L1timer() by calls to the
newly introduced bcma_core_pci_ip() and bcma_core_pci_down()
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Arend van Spriel <arend@broadcom.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This fix has been discussed with Hauke Mehrtens [1] selection
option 3) and is intended for v3.12.
Ref:
[1] http://mid.gmane.org/5239B12D.3040206@hauke-m.de
Cc: <stable@vger.kernel.org> # 3.11.x
Cc: Tod Jackson <tod.jackson@gmail.com>
Cc: Joe Perches <joe@perches.com>
Cc: Rafal Milecki <zajec5@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Reviewed-by: Hante Meuleman <meuleman@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
336 lines
8.9 KiB
C
336 lines
8.9 KiB
C
/*
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* Broadcom specific AMBA
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* PCI Core
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*
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* Copyright 2005, 2011, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/export.h>
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#include <linux/bcma/bcma.h>
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/**************************************************
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* R/W ops.
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**************************************************/
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u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
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{
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
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}
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static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
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{
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
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pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
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}
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static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
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{
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u32 v;
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int i;
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_WRITE;
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v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
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BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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v |= (phy << 4);
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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udelay(10);
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for (i = 0; i < 200; i++) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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usleep_range(1000, 2000);
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}
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}
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static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
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{
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int max_retries = 10;
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u16 ret = 0;
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u32 v;
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int i;
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/* enable mdio access to SERDES */
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v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
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v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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} else {
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v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
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}
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_READ;
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
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udelay(10);
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ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
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break;
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}
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usleep_range(1000, 2000);
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}
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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return ret;
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}
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static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
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u8 address, u16 data)
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{
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int max_retries = 10;
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u32 v;
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int i;
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/* enable mdio access to SERDES */
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v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
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v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
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if (pc->core->id.rev >= 10) {
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max_retries = 200;
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bcma_pcie_mdio_set_phy(pc, device);
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v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
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BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
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} else {
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v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
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v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
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}
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v = BCMA_CORE_PCI_MDIODATA_START;
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v |= BCMA_CORE_PCI_MDIODATA_WRITE;
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v |= BCMA_CORE_PCI_MDIODATA_TA;
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v |= data;
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
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/* Wait for the device to complete the transaction */
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udelay(10);
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for (i = 0; i < max_retries; i++) {
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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usleep_range(1000, 2000);
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}
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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}
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static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
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u8 address, u16 data)
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{
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bcma_pcie_mdio_write(pc, device, address, data);
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return bcma_pcie_mdio_read(pc, device, address);
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}
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/**************************************************
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* Workarounds.
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**************************************************/
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static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
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{
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u32 tmp;
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tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
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if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
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return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
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BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
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else
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return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
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}
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static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
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{
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u16 tmp;
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bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
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BCMA_CORE_PCI_SERDES_RX_CTRL,
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bcma_pcicore_polarity_workaround(pc));
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tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
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BCMA_CORE_PCI_SERDES_PLL_CTRL);
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if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
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bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
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BCMA_CORE_PCI_SERDES_PLL_CTRL,
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tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
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}
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static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
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{
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struct bcma_device *core = pc->core;
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u16 val16, core_index;
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uint regoff;
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regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
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core_index = (u16)core->core_index;
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val16 = pcicore_read16(pc, regoff);
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if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
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!= core_index) {
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val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
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(val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
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pcicore_write16(pc, regoff, val16);
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}
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}
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/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
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/* Needs to happen when coming out of 'standby'/'hibernate' */
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static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
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{
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u16 val16;
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uint regoff;
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regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
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val16 = pcicore_read16(pc, regoff);
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if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
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val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
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pcicore_write16(pc, regoff, val16);
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}
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}
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/**************************************************
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* Init.
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**************************************************/
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static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
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{
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bcma_core_pci_fixcfg(pc);
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bcma_pcicore_serdes_workaround(pc);
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bcma_core_pci_config_fixup(pc);
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}
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void bcma_core_pci_init(struct bcma_drv_pci *pc)
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{
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if (pc->setup_done)
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return;
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
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if (pc->hostmode)
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bcma_core_pci_hostmode_init(pc);
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#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
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if (!pc->hostmode)
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bcma_core_pci_clientmode_init(pc);
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}
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void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
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{
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struct bcma_drv_pci *pc;
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u16 data;
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if (bus->hosttype != BCMA_HOSTTYPE_PCI)
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return;
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pc = &bus->drv_pci[0];
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if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
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data = up ? 0x74 : 0x7C;
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bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
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bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
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} else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
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data = up ? 0x75 : 0x7D;
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bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
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bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
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BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
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}
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
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int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
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bool enable)
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{
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struct pci_dev *pdev;
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u32 coremask, tmp;
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int err = 0;
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if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
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/* This bcma device is not on a PCI host-bus. So the IRQs are
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* not routed through the PCI core.
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* So we must not enable routing through the PCI core. */
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goto out;
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}
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pdev = pc->core->bus->host_pci;
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err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
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if (err)
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goto out;
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coremask = BIT(core->core_index) << 8;
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if (enable)
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tmp |= coremask;
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else
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tmp &= ~coremask;
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err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
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out:
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return err;
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
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static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
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{
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u32 w;
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w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
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if (extend)
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w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
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else
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w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
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bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
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bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
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}
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void bcma_core_pci_up(struct bcma_bus *bus)
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{
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struct bcma_drv_pci *pc;
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if (bus->hosttype != BCMA_HOSTTYPE_PCI)
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return;
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pc = &bus->drv_pci[0];
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bcma_core_pci_extend_L1timer(pc, true);
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_up);
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void bcma_core_pci_down(struct bcma_bus *bus)
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{
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struct bcma_drv_pci *pc;
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if (bus->hosttype != BCMA_HOSTTYPE_PCI)
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return;
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pc = &bus->drv_pci[0];
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bcma_core_pci_extend_L1timer(pc, false);
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}
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EXPORT_SYMBOL_GPL(bcma_core_pci_down);
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