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444bddc4b9
This allows you to look at the current DPM state via debugfs. Due to the way the hardware works on these asics, there's no way to look up exactly what power state we are in, so we make the best guess we can based on the current sclk. v2: Anthoine's version v3: fix ref div Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
172 lines
7.3 KiB
C
172 lines
7.3 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __RS780D_H__
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#define __RS780D_H__
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#define CG_SPLL_FUNC_CNTL 0x600
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# define SPLL_RESET (1 << 0)
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# define SPLL_SLEEP (1 << 1)
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# define SPLL_REF_DIV(x) ((x) << 2)
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# define SPLL_REF_DIV_MASK (7 << 2)
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# define SPLL_REF_DIV_SHIFT 2
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# define SPLL_FB_DIV(x) ((x) << 5)
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# define SPLL_FB_DIV_MASK (0xff << 2)
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# define SPLL_FB_DIV_SHIFT 2
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# define SPLL_PULSEEN (1 << 13)
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# define SPLL_PULSENUM(x) ((x) << 14)
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# define SPLL_PULSENUM_MASK (3 << 14)
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# define SPLL_SW_HILEN(x) ((x) << 16)
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# define SPLL_SW_HILEN_MASK (0xf << 16)
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# define SPLL_SW_HILEN_SHIFT 16
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# define SPLL_SW_LOLEN(x) ((x) << 20)
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# define SPLL_SW_LOLEN_MASK (0xf << 20)
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# define SPLL_SW_LOLEN_SHIFT 20
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# define SPLL_DIVEN (1 << 24)
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# define SPLL_BYPASS_EN (1 << 25)
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# define SPLL_CHG_STATUS (1 << 29)
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# define SPLL_CTLREQ (1 << 30)
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# define SPLL_CTLACK (1 << 31)
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/* RS780/RS880 PM */
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#define FVTHROT_CNTRL_REG 0x3000
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#define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
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#define MINIMUM_CIP(x) ((x) << 1)
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#define MINIMUM_CIP_SHIFT 1
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#define MINIMUM_CIP_MASK 0x1fffffe
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#define REFRESH_RATE_DIVISOR(x) ((x) << 25)
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#define REFRESH_RATE_DIVISOR_SHIFT 25
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#define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
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#define ENABLE_FV_THROT (1 << 27)
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#define ENABLE_FV_UPDATE (1 << 28)
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#define TREND_SEL_MODE (1 << 29)
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#define FORCE_TREND_SEL (1 << 30)
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#define ENABLE_FV_THROT_IO (1 << 31)
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#define FVTHROT_TARGET_REG 0x3004
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#define TARGET_IDLE_COUNT(x) ((x) << 0)
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#define TARGET_IDLE_COUNT_MASK 0xffffff
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#define TARGET_IDLE_COUNT_SHIFT 0
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#define FVTHROT_CB1 0x3008
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#define FVTHROT_CB2 0x300c
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#define FVTHROT_CB3 0x3010
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#define FVTHROT_CB4 0x3014
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#define FVTHROT_UTC0 0x3018
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#define FVTHROT_UTC1 0x301c
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#define FVTHROT_UTC2 0x3020
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#define FVTHROT_UTC3 0x3024
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#define FVTHROT_UTC4 0x3028
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#define FVTHROT_DTC0 0x302c
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#define FVTHROT_DTC1 0x3030
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#define FVTHROT_DTC2 0x3034
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#define FVTHROT_DTC3 0x3038
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#define FVTHROT_DTC4 0x303c
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#define FVTHROT_FBDIV_REG0 0x3040
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#define MIN_FEEDBACK_DIV(x) ((x) << 0)
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#define MIN_FEEDBACK_DIV_MASK 0xfff
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#define MIN_FEEDBACK_DIV_SHIFT 0
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#define MAX_FEEDBACK_DIV(x) ((x) << 12)
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#define MAX_FEEDBACK_DIV_MASK (0xfff << 12)
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#define MAX_FEEDBACK_DIV_SHIFT 12
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#define FVTHROT_FBDIV_REG1 0x3044
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#define MAX_FEEDBACK_STEP(x) ((x) << 0)
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#define MAX_FEEDBACK_STEP_MASK 0xfff
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#define MAX_FEEDBACK_STEP_SHIFT 0
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#define STARTING_FEEDBACK_DIV(x) ((x) << 12)
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#define STARTING_FEEDBACK_DIV_MASK (0xfff << 12)
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#define STARTING_FEEDBACK_DIV_SHIFT 12
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#define FORCE_FEEDBACK_DIV (1 << 24)
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#define FVTHROT_FBDIV_REG2 0x3048
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#define FORCED_FEEDBACK_DIV(x) ((x) << 0)
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#define FORCED_FEEDBACK_DIV_MASK 0xfff
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#define FORCED_FEEDBACK_DIV_SHIFT 0
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#define FB_DIV_TIMER_VAL(x) ((x) << 12)
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#define FB_DIV_TIMER_VAL_MASK (0xffff << 12)
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#define FB_DIV_TIMER_VAL_SHIFT 12
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#define FVTHROT_FB_US_REG0 0x304c
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#define FVTHROT_FB_US_REG1 0x3050
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#define FVTHROT_FB_DS_REG0 0x3054
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#define FVTHROT_FB_DS_REG1 0x3058
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#define FVTHROT_PWM_CTRL_REG0 0x305c
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#define STARTING_PWM_HIGHTIME(x) ((x) << 0)
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#define STARTING_PWM_HIGHTIME_MASK 0xfff
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#define STARTING_PWM_HIGHTIME_SHIFT 0
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#define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12)
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#define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12)
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#define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12
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#define FORCE_STARTING_PWM_HIGHTIME (1 << 24)
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#define INVERT_PWM_WAVEFORM (1 << 25)
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#define FVTHROT_PWM_CTRL_REG1 0x3060
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#define MIN_PWM_HIGHTIME(x) ((x) << 0)
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#define MIN_PWM_HIGHTIME_MASK 0xfff
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#define MIN_PWM_HIGHTIME_SHIFT 0
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#define MAX_PWM_HIGHTIME(x) ((x) << 12)
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#define MAX_PWM_HIGHTIME_MASK (0xfff << 12)
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#define MAX_PWM_HIGHTIME_SHIFT 12
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#define FVTHROT_PWM_US_REG0 0x3064
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#define FVTHROT_PWM_US_REG1 0x3068
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#define FVTHROT_PWM_DS_REG0 0x306c
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#define FVTHROT_PWM_DS_REG1 0x3070
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#define FVTHROT_STATUS_REG0 0x3074
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#define CURRENT_FEEDBACK_DIV_MASK 0xfff
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#define CURRENT_FEEDBACK_DIV_SHIFT 0
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#define FVTHROT_STATUS_REG1 0x3078
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#define FVTHROT_STATUS_REG2 0x307c
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#define CG_INTGFX_MISC 0x3080
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#define FVTHROT_VBLANK_SEL (1 << 9)
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#define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c
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#define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0)
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#define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff
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#define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0
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#define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12)
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#define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090
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#define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0)
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#define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff
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#define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0
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#define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12)
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#define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12)
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#define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12
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#define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094
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#define RANGE0_PWM(x) ((x) << 0)
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#define RANGE0_PWM_MASK 0xfff
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#define RANGE0_PWM_SHIFT 0
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#define RANGE1_PWM(x) ((x) << 12)
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#define RANGE1_PWM_MASK (0xfff << 12)
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#define RANGE1_PWM_SHIFT 12
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#define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098
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#define RANGE2_PWM(x) ((x) << 0)
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#define RANGE2_PWM_MASK 0xfff
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#define RANGE2_PWM_SHIFT 0
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#define RANGE3_PWM(x) ((x) << 12)
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#define RANGE3_PWM_MASK (0xfff << 12)
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#define RANGE3_PWM_SHIFT 12
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#define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac
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#define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0)
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#define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff
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#define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0
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#define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12)
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#define GFX_MACRO_BYPASS_CNTL 0x30c0
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#define SPLL_BYPASS_CNTL (1 << 0)
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#define UPLL_BYPASS_CNTL (1 << 1)
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#endif
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