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https://github.com/edk2-porting/linux-next.git
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6645cb61f3
Commit 66a625a (ARM: mm: proc-macros: Add generic proc/cache/tlb struct
definition macros) introduced build errors when PM_SLEEP is not enabled.
The per-CPU do_suspend/do_resume functions are defined via the
preprocessor to constant 0. However, the macros which use these were
converted to assembly, resulting in undefined references to these
functions. Fix that by moving the ! ifdef section into proc-macros.S
and deleting it from all effected proc-*.S files.
Acked-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
325 lines
7.6 KiB
ArmAsm
325 lines
7.6 KiB
ArmAsm
/*
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* We need constants.h for:
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* VMA_VM_MM
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* VMA_VM_FLAGS
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* VM_EXEC
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*/
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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/*
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* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
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*/
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.macro vma_vm_mm, rd, rn
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ldr \rd, [\rn, #VMA_VM_MM]
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.endm
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/*
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* vma_vm_flags - get vma->vm_flags
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*/
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.macro vma_vm_flags, rd, rn
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ldr \rd, [\rn, #VMA_VM_FLAGS]
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.endm
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.macro tsk_mm, rd, rn
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ldr \rd, [\rn, #TI_TASK]
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ldr \rd, [\rd, #TSK_ACTIVE_MM]
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.endm
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/*
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* act_mm - get current->active_mm
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*/
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.macro act_mm, rd
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bic \rd, sp, #8128
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bic \rd, \rd, #63
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ldr \rd, [\rd, #TI_TASK]
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ldr \rd, [\rd, #TSK_ACTIVE_MM]
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.endm
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/*
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* mmid - get context id from mm pointer (mm->context.id)
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*/
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.macro mmid, rd, rn
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ldr \rd, [\rn, #MM_CONTEXT_ID]
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.endm
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/*
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* mask_asid - mask the ASID from the context ID
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*/
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.macro asid, rd, rn
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and \rd, \rn, #255
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.endm
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.macro crval, clear, mmuset, ucset
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#ifdef CONFIG_MMU
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.word \clear
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.word \mmuset
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#else
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.word \clear
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.word \ucset
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#endif
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.endm
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/*
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* dcache_line_size - get the minimum D-cache line size from the CTR register
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* on ARMv7.
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*/
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.macro dcache_line_size, reg, tmp
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mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
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lsr \tmp, \tmp, #16
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and \tmp, \tmp, #0xf @ cache line size encoding
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mov \reg, #4 @ bytes per word
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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/*
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* icache_line_size - get the minimum I-cache line size from the CTR register
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* on ARMv7.
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*/
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.macro icache_line_size, reg, tmp
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mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
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and \tmp, \tmp, #0xf @ cache line size encoding
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mov \reg, #4 @ bytes per word
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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/*
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* Sanity check the PTE configuration for the code below - which makes
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* certain assumptions about how these bits are laid out.
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*/
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#ifdef CONFIG_MMU
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#if L_PTE_SHARED != PTE_EXT_SHARED
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#error PTE shared bit mismatch
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#endif
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#if (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
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L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
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#error Invalid Linux PTE bit settings
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#endif
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#endif /* CONFIG_MMU */
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/*
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* The ARMv6 and ARMv7 set_pte_ext translation function.
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*
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* Permission translation:
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* YUWD APX AP1 AP0 SVC User
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* 0xxx 0 0 0 no acc no acc
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* 100x 1 0 1 r/o no acc
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* 10x0 1 0 1 r/o no acc
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* 1011 0 0 1 r/w no acc
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* 110x 0 1 0 r/w r/o
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* 11x0 0 1 0 r/w r/o
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* 1111 0 1 1 r/w r/w
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*
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* If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
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* 110x 1 1 1 r/o r/o
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* 11x0 1 1 1 r/o r/o
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*/
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.macro armv6_mt_table pfx
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\pfx\()_mt_table:
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.long 0x00 @ L_PTE_MT_UNCACHED
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.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
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.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ unused
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.long 0x00 @ L_PTE_MT_MINICACHE (not present)
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
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.long 0x00 @ unused
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.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.endm
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.macro armv6_set_pte_ext pfx
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str r1, [r0], #2048 @ linux version
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bic r3, r1, #0x000003fc
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bic r3, r3, #PTE_TYPE_MASK
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orr r3, r3, r2
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orr r3, r3, #PTE_EXT_AP0 | 2
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adr ip, \pfx\()_mt_table
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and r2, r1, #L_PTE_MT_MASK
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ldr r2, [ip, r2]
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eor r1, r1, #L_PTE_DIRTY
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tst r1, #L_PTE_DIRTY|L_PTE_RDONLY
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orrne r3, r3, #PTE_EXT_APX
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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#ifdef CONFIG_CPU_USE_DOMAINS
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@ allow kernel read/write access to read-only user pages
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tstne r3, #PTE_EXT_APX
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bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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#endif
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tst r1, #L_PTE_XN
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orrne r3, r3, #PTE_EXT_XN
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orr r3, r3, r2
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_PRESENT
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moveq r3, #0
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str r3, [r0]
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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.endm
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/*
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* The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
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* covering most CPUs except Xscale and Xscale 3.
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*
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* Permission translation:
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* YUWD AP SVC User
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* 0xxx 0x00 no acc no acc
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* 100x 0x00 r/o no acc
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* 10x0 0x00 r/o no acc
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* 1011 0x55 r/w no acc
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* 110x 0xaa r/w r/o
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* 11x0 0xaa r/w r/o
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* 1111 0xff r/w r/w
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*/
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.macro armv3_set_pte_ext wc_disable=1
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str r1, [r0], #2048 @ linux version
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eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
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bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
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bic r2, r2, #PTE_TYPE_MASK
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orr r2, r2, #PTE_TYPE_SMALL
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tst r3, #L_PTE_USER @ user?
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orrne r2, r2, #PTE_SMALL_AP_URO_SRW
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tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
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orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
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tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
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movne r2, #0
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.if \wc_disable
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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tst r2, #PTE_CACHEABLE
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bicne r2, r2, #PTE_BUFFERABLE
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#endif
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.endif
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str r2, [r0] @ hardware version
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.endm
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/*
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* Xscale set_pte_ext translation, split into two halves to cope
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* with work-arounds. r3 must be preserved by code between these
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* two macros.
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*
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* Permission translation:
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* YUWD AP SVC User
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* 0xxx 00 no acc no acc
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* 100x 00 r/o no acc
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* 10x0 00 r/o no acc
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* 1011 01 r/w no acc
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* 110x 10 r/w r/o
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* 11x0 10 r/w r/o
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* 1111 11 r/w r/w
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*/
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.macro xscale_set_pte_ext_prologue
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str r1, [r0] @ linux version
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eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
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bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
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orr r2, r2, #PTE_TYPE_EXT @ extended page
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tst r3, #L_PTE_USER @ user?
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orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
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tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
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orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
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@ combined with user -> user r/w
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.endm
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.macro xscale_set_pte_ext_epilogue
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tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
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movne r2, #0 @ no -> fault
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str r2, [r0, #2048]! @ hardware version
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mov ip, #0
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mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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.endm
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.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0
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.type \name\()_processor_functions, #object
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.align 2
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ENTRY(\name\()_processor_functions)
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.word \dabort
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.word \pabort
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.word cpu_\name\()_proc_init
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.word cpu_\name\()_proc_fin
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.word cpu_\name\()_reset
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.word cpu_\name\()_do_idle
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.word cpu_\name\()_dcache_clean_area
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.word cpu_\name\()_switch_mm
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.if \nommu
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.word 0
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.else
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.word cpu_\name\()_set_pte_ext
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.endif
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.if \suspend
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.word cpu_\name\()_suspend_size
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#ifdef CONFIG_PM_SLEEP
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.word cpu_\name\()_do_suspend
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.word cpu_\name\()_do_resume
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#else
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.word 0
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.word 0
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#endif
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.else
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.word 0
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.word 0
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.word 0
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.endif
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.size \name\()_processor_functions, . - \name\()_processor_functions
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.endm
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.macro define_cache_functions name:req
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.align 2
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.type \name\()_cache_fns, #object
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ENTRY(\name\()_cache_fns)
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.long \name\()_flush_icache_all
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.long \name\()_flush_kern_cache_all
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.long \name\()_flush_user_cache_all
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.long \name\()_flush_user_cache_range
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.long \name\()_coherent_kern_range
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.long \name\()_coherent_user_range
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.long \name\()_flush_kern_dcache_area
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.long \name\()_dma_map_area
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.long \name\()_dma_unmap_area
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.long \name\()_dma_flush_range
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.size \name\()_cache_fns, . - \name\()_cache_fns
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.endm
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.macro define_tlb_functions name:req, flags_up:req, flags_smp
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.type \name\()_tlb_fns, #object
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ENTRY(\name\()_tlb_fns)
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.long \name\()_flush_user_tlb_range
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.long \name\()_flush_kern_tlb_range
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.ifnb \flags_smp
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ALT_SMP(.long \flags_smp )
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ALT_UP(.long \flags_up )
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.else
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.long \flags_up
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.endif
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.size \name\()_tlb_fns, . - \name\()_tlb_fns
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.endm
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