2
0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-25 13:43:55 +08:00
linux-next/drivers/clk/renesas
Simon Horman 71119b54a2 clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents
Support Z and Z2 clocks with parent frequencies greater than UINT32_MAX Hz
(~4.29GHz).

The DIV_ROUND_CLOSEST_ULL() macro accepts a 64bit dividend and 32bit
divisor. This leads to truncation of the divisor, which is the Z or Z2
parent clock frequency in HZ, on platforms where frequency of that clock is
greater than UINT32_MAX Hz.

To resolve this problem the DIV64_U64_ROUND_CLOSEST() macro, which takes
on an unsigned 64bit dividend and divisor, is used.

An earlier version of this patch made use of the existing
DIV_ROUND_CLOSEST() macro, which accepts the prevailing type of the
dividend and divisor. However, this does not compile on 32bit systems, such
as i386 and mips, when called with the types used at this call site, an
unsigned long long dividend and unsigned long divisor.

This work is in preparation for supporting the Z2 clock on the
R-Car Gen3 E3 (r8a77990) SoC which has a 4.8GHz parent clock.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02 09:50:48 +02:00
..
clk-div6.c clk: renesas: Remove usage of CLK_IS_BASIC 2018-12-10 14:43:04 -08:00
clk-div6.h We have two changes to the core framework this time around. The first being a 2017-11-17 20:04:24 -08:00
clk-emev2.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-mstp.c Merge branch 'clk-of' into clk-next 2018-12-14 14:02:55 -08:00
clk-r8a73a4.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-r8a7740.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-r8a7778.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-r8a7779.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-rcar-gen2.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-rz.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-sh73a0.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
Kconfig Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00
Makefile clk: renesas: cpg-mssr: Add r8a774c0 support 2018-09-19 16:42:14 +02:00
r7s9210-cpg-mssr.c clk: renesas: r7s9210: Always use readl() 2019-04-02 09:50:48 +02:00
r8a774a1-cpg-mssr.c clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 2019-04-02 09:50:48 +02:00
r8a774c0-cpg-mssr.c clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK 2019-02-21 13:09:52 -08:00
r8a7743-cpg-mssr.c Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00
r8a7745-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7790-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7791-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7792-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7794-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7795-cpg-mssr.c clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 2019-04-02 09:50:48 +02:00
r8a7796-cpg-mssr.c clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 2019-04-02 09:50:48 +02:00
r8a77470-cpg-mssr.c clk: renesas: cpg-mssr: Add r8a77470 support 2018-04-16 13:39:40 +02:00
r8a77965-cpg-mssr.c clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset 2019-04-02 09:50:48 +02:00
r8a77970-cpg-mssr.c clk: renesas: r8a77970: Add CPEX clock 2018-12-04 10:29:48 +01:00
r8a77980-cpg-mssr.c clk: renesas: r8a77980: Add RPC clocks 2019-02-05 10:40:05 +01:00
r8a77990-cpg-mssr.c clk: renesas: r8a77990: Correct parent clock of DU 2018-12-04 10:29:51 +01:00
r8a77995-cpg-mssr.c clk: renesas: r8a77995: Simplify PLL3 multiplier/divider 2018-12-04 10:30:16 +01:00
r9a06g032-clocks.c clk: renesas: r9a06g032: Add missing PCI USB clock 2019-04-02 09:50:48 +02:00
rcar-gen2-cpg.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
rcar-gen2-cpg.h clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
rcar-gen3-cpg.c clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents 2019-04-02 09:50:48 +02:00
rcar-gen3-cpg.h clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 2019-04-02 09:50:48 +02:00
rcar-usb2-clock-sel.c clk: renesas: use SPDX identifier for Renesas drivers 2018-08-30 18:18:44 -07:00
renesas-cpg-mssr.c clk: renesas: Remove usage of CLK_IS_BASIC 2018-12-10 14:43:04 -08:00
renesas-cpg-mssr.h Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00