mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-28 15:13:55 +08:00
d2885dbb7a
Add card detect gpio for SD card slot and include dt gpio header. Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
370 lines
9.7 KiB
Plaintext
370 lines
9.7 KiB
Plaintext
/*
|
|
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
/* AM43x EPOS EVM */
|
|
|
|
/dts-v1/;
|
|
|
|
#include "am4372.dtsi"
|
|
#include <dt-bindings/pinctrl/am43xx.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/pwm/pwm.h>
|
|
|
|
/ {
|
|
model = "TI AM43x EPOS EVM";
|
|
compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
|
|
|
|
vmmcsd_fixed: fixedregulator-sd {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vmmcsd_fixed";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
enable-active-high;
|
|
};
|
|
|
|
am43xx_pinmux: pinmux@44e10800 {
|
|
cpsw_default: cpsw_default {
|
|
pinctrl-single,pins = <
|
|
/* Slave 1 */
|
|
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
|
|
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
|
|
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
|
|
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
|
|
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
|
|
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
|
|
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
|
|
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
|
|
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
|
|
>;
|
|
};
|
|
|
|
cpsw_sleep: cpsw_sleep {
|
|
pinctrl-single,pins = <
|
|
/* Slave 1 reset value */
|
|
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
>;
|
|
};
|
|
|
|
davinci_mdio_default: davinci_mdio_default {
|
|
pinctrl-single,pins = <
|
|
/* MDIO */
|
|
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
|
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
|
>;
|
|
};
|
|
|
|
davinci_mdio_sleep: davinci_mdio_sleep {
|
|
pinctrl-single,pins = <
|
|
/* MDIO reset value */
|
|
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
>;
|
|
};
|
|
|
|
i2c0_pins: pinmux_i2c0_pins {
|
|
pinctrl-single,pins = <
|
|
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
|
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
|
>;
|
|
};
|
|
|
|
nand_flash_x8: nand_flash_x8 {
|
|
pinctrl-single,pins = <
|
|
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
|
|
0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
|
0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
|
0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
|
0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
|
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
|
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
|
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
|
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
|
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
|
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
|
|
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
|
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
|
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
|
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
|
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
|
>;
|
|
};
|
|
|
|
ecap0_pins: backlight_pins {
|
|
pinctrl-single,pins = <
|
|
0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
|
|
>;
|
|
};
|
|
|
|
i2c2_pins: pinmux_i2c2_pins {
|
|
pinctrl-single,pins = <
|
|
0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
|
|
0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
|
|
>;
|
|
};
|
|
|
|
spi0_pins: pinmux_spi0_pins {
|
|
pinctrl-single,pins = <
|
|
0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
|
|
0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
|
|
0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
|
|
0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
|
|
>;
|
|
};
|
|
|
|
spi1_pins: pinmux_spi1_pins {
|
|
pinctrl-single,pins = <
|
|
0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
|
|
0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
|
|
0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
|
|
0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
|
|
>;
|
|
};
|
|
|
|
mmc1_pins: pinmux_mmc1_pins {
|
|
pinctrl-single,pins = <
|
|
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
|
>;
|
|
};
|
|
};
|
|
|
|
matrix_keypad: matrix_keypad@0 {
|
|
compatible = "gpio-matrix-keypad";
|
|
debounce-delay-ms = <5>;
|
|
col-scan-delay-us = <2>;
|
|
|
|
row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
|
|
&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
|
|
&gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
|
|
&gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
|
|
|
|
col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
|
|
&gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
|
|
&gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
|
|
&gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
|
|
|
|
linux,keymap = <0x00000201 /* P1 */
|
|
0x01000204 /* P4 */
|
|
0x02000207 /* P7 */
|
|
0x0300020a /* NUMERIC_STAR */
|
|
0x00010202 /* P2 */
|
|
0x01010205 /* P5 */
|
|
0x02010208 /* P8 */
|
|
0x03010200 /* P0 */
|
|
0x00020203 /* P3 */
|
|
0x01020206 /* P6 */
|
|
0x02020209 /* P9 */
|
|
0x0302020b /* NUMERIC_POUND */
|
|
0x00030067 /* UP */
|
|
0x0103006a /* RIGHT */
|
|
0x0203006c /* DOWN */
|
|
0x03030069>; /* LEFT */
|
|
};
|
|
|
|
backlight {
|
|
compatible = "pwm-backlight";
|
|
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
|
|
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
|
default-brightness-level = <8>;
|
|
};
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
vmmc-supply = <&vmmcsd_fixed>;
|
|
bus-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins>;
|
|
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
&mac {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&cpsw_default>;
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
status = "okay";
|
|
};
|
|
|
|
&davinci_mdio {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
status = "okay";
|
|
};
|
|
|
|
&cpsw_emac0 {
|
|
phy_id = <&davinci_mdio>, <16>;
|
|
phy-mode = "rmii";
|
|
};
|
|
|
|
&cpsw_emac1 {
|
|
phy_id = <&davinci_mdio>, <1>;
|
|
phy-mode = "rmii";
|
|
};
|
|
|
|
&i2c0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
|
|
at24@50 {
|
|
compatible = "at24,24c256";
|
|
pagesize = <64>;
|
|
reg = <0x50>;
|
|
};
|
|
|
|
pixcir_ts@5c {
|
|
compatible = "pixcir,pixcir_ts";
|
|
reg = <0x5c>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <17 0>;
|
|
|
|
attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
|
|
|
|
x-size = <1024>;
|
|
y-size = <768>;
|
|
};
|
|
};
|
|
|
|
&i2c2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&elm {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpmc {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&nand_flash_x8>;
|
|
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
|
|
nand@0,0 {
|
|
reg = <0 0 0>; /* CS0, offset 0 */
|
|
ti,nand-ecc-opt = "bch8";
|
|
ti,elm-id = <&elm>;
|
|
nand-bus-width = <8>;
|
|
gpmc,device-width = <1>;
|
|
gpmc,sync-clk-ps = <0>;
|
|
gpmc,cs-on-ns = <0>;
|
|
gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
|
|
gpmc,cs-wr-off-ns = <40>;
|
|
gpmc,adv-on-ns = <0>; /* cs-on-ns */
|
|
gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
|
|
gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
|
|
gpmc,we-on-ns = <0>; /* cs-on-ns */
|
|
gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
|
|
gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
|
|
gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
|
|
gpmc,access-ns = <30>; /* tCEA + 4*/
|
|
gpmc,rd-cycle-ns = <40>;
|
|
gpmc,wr-cycle-ns = <40>;
|
|
gpmc,wait-on-read = "true";
|
|
gpmc,wait-on-write = "true";
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
gpmc,clk-activation-ns = <0>;
|
|
gpmc,wait-monitoring-ns = <0>;
|
|
gpmc,wr-access-ns = <40>;
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
/* MTD partition table */
|
|
/* All SPL-* partitions are sized to minimal length
|
|
* which can be independently programmable. For
|
|
* NAND flash this is equal to size of erase-block */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
partition@0 {
|
|
label = "NAND.SPL";
|
|
reg = <0x00000000 0x00040000>;
|
|
};
|
|
partition@1 {
|
|
label = "NAND.SPL.backup1";
|
|
reg = <0x00040000 0x00040000>;
|
|
};
|
|
partition@2 {
|
|
label = "NAND.SPL.backup2";
|
|
reg = <0x00080000 0x00040000>;
|
|
};
|
|
partition@3 {
|
|
label = "NAND.SPL.backup3";
|
|
reg = <0x000C0000 0x00040000>;
|
|
};
|
|
partition@4 {
|
|
label = "NAND.u-boot-spl-os";
|
|
reg = <0x00100000 0x00080000>;
|
|
};
|
|
partition@5 {
|
|
label = "NAND.u-boot";
|
|
reg = <0x00180000 0x00100000>;
|
|
};
|
|
partition@6 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x00280000 0x00040000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env.backup1";
|
|
reg = <0x002C0000 0x00040000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00300000 0x00700000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00800000 0x1F600000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&epwmss0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&ecap0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ecap0_pins>;
|
|
};
|
|
|
|
&spi0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&spi1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_pins>;
|
|
status = "okay";
|
|
};
|