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7017ff0ee1
To implement the get/set_irqchip_state callbacks (limited to the PENDING state), we have to use a particular set of hacks: - Reading the pending state is done by using a pair of new redistributor registers (GICR_VSGIR, GICR_VSGIPENDR), which allow the 16 interrupts state to be retrieved. - Setting the pending state is done by generating it as we'd otherwise do for a guest (writing to GITS_SGIR). - Clearing the pending state is done by emitting a VSGI command with the "clear" bit set. This requires some interesting locking though: - When talking to the redistributor, we must make sure that the VPE affinity doesn't change, hence taking the VPE lock. - At the same time, we must ensure that nobody accesses the same redistributor's GICR_VSGIR registers for a different VPE, which would corrupt the reading of the pending bits. We thus take the per-RD spinlock. Much fun. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Link: https://lore.kernel.org/r/20200304203330.4967-12-maz@kernel.org |
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| .. | ||
| arm-gic-common.h | ||
| arm-gic-v3.h | ||
| arm-gic-v4.h | ||
| arm-gic.h | ||
| arm-vic.h | ||
| chained_irq.h | ||
| irq-bcm2836.h | ||
| irq-davinci-aintc.h | ||
| irq-davinci-cp-intc.h | ||
| irq-ixp4xx.h | ||
| irq-madera.h | ||
| irq-omap-intc.h | ||
| irq-partition-percpu.h | ||
| irq-sa11x0.h | ||
| mmp.h | ||
| mxs.h | ||
| versatile-fpga.h | ||
| xtensa-mx.h | ||
| xtensa-pic.h | ||