mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-30 08:04:13 +08:00
afe6fe7036
Here are two branches that came relatively late during the linux-5.0
development cycle and have dependencies on the other branches:
- On the TI OMAP platform, the CPSW Ethernet PHY mode selection driver
is being replaced, this puts the final pieces in place
- On the DaVinci platform, the interrupt handling code in arch/arm
gets moved into a regular device driver in drivers/irqchip.
Since they both had some time in linux-next after the 5.0-rc8
release, I'm sending them along with the other updates.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC late updates from Arnd Bergmann:
"Here are two branches that came relatively late during the linux-5.0
development cycle and have dependencies on the other branches:
- On the TI OMAP platform, the CPSW Ethernet PHY mode selection
driver is being replaced, this puts the final pieces in place
- On the DaVinci platform, the interrupt handling code in arch/arm
gets moved into a regular device driver in drivers/irqchip.
Since they both had some time in linux-next after the 5.0-rc8 release,
I'm sending them along with the other updates"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
net: ethernet: ti: cpsw: deprecate cpsw-phy-sel driver
ARM: davinci: remove intc related fields from davinci_soc_info
irqchip: davinci-cp-intc: move the driver to drivers/irqchip
ARM: davinci: cp-intc: remove redundant comments
ARM: davinci: cp-intc: drop GPL license boilerplate
ARM: davinci: cp-intc: use readl/writel_relaxed()
ARM: davinci: cp-intc: unify error handling
ARM: davinci: cp-intc: improve coding style
ARM: davinci: cp-intc: request the memory region before remapping it
ARM: davinci: cp-intc: use the new-style config structure
ARM: davinci: cp-intc: convert all hex numbers to lowercase
ARM: davinci: cp-intc: use a common prefix for all symbols
ARM: davinci: cp-intc: add the new config structures for da8xx SoCs
irqchip: davinci-cp-intc: add a new config structure
ARM: davinci: cp-intc: add a wrapper around cp_intc_init()
ARM: davinci: cp-intc: remove cp_intc.h
irqchip: davinci-aintc: move the driver to drivers/irqchip
ARM: davinci: aintc: remove unnecessary includes
ARM: davinci: aintc: remove the timer-specific irq_set_handler()
ARM: davinci: aintc: request memory region before remapping it
...
441 lines
8.4 KiB
Plaintext
441 lines
8.4 KiB
Plaintext
menu "IRQ chip support"
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config IRQCHIP
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def_bool y
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depends on OF_IRQ
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config ARM_GIC
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bool
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_MULTI_HANDLER
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ARM_GIC_PM
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bool
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depends on PM
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select ARM_GIC
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select PM_CLK
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config ARM_GIC_MAX_NR
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int
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default 2 if ARCH_REALVIEW
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default 1
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config ARM_GIC_V2M
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bool
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depends on PCI
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select ARM_GIC
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select PCI_MSI
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config GIC_NON_BANKED
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bool
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config ARM_GIC_V3
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select IRQ_DOMAIN_HIERARCHY
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select PARTITION_PERCPU
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ARM_GIC_V3_ITS
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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default ARM_GIC_V3
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config ARM_GIC_V3_ITS_PCI
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bool
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depends on ARM_GIC_V3_ITS
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depends on PCI
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depends on PCI_MSI
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default ARM_GIC_V3_ITS
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config ARM_GIC_V3_ITS_FSL_MC
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bool
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depends on ARM_GIC_V3_ITS
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depends on FSL_MC_BUS
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default ARM_GIC_V3_ITS
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config ARM_NVIC
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bool
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_CHIP
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config ARM_VIC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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config ARMADA_370_XP_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select PCI_MSI if PCI
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ALPINE_MSI
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bool
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depends on PCI
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select PCI_MSI
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select GENERIC_IRQ_CHIP
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select SPARSE_IRQ
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config ATMEL_AIC5_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select SPARSE_IRQ
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config I8259
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bool
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select IRQ_DOMAIN
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config BCM6345_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config BCM7038_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config BCM7120_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config BRCMSTB_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DAVINCI_AINTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DAVINCI_CP_INTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DW_APB_ICTL
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config FARADAY_FTINTC010
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select SPARSE_IRQ
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config HISILICON_IRQ_MBIGEN
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bool
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select ARM_GIC_V3
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select ARM_GIC_V3_ITS
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config IMGPDC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config MADERA_IRQ
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tristate
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config IRQ_MIPS_CPU
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bool
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select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config CLPS711X_IRQCHIP
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bool
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depends on ARCH_CLPS711X
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select SPARSE_IRQ
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default y
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config OMPIC
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bool
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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config OMAP_IRQCHIP
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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config PIC32_EVIC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config JCORE_AIC
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bool "J-Core integrated AIC" if COMPILE_TEST
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depends on OF
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select IRQ_DOMAIN
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help
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Support for the J-Core integrated AIC.
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config RDA_INTC
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bool
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select IRQ_DOMAIN
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config RENESAS_INTC_IRQPIN
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bool
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select IRQ_DOMAIN
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config RENESAS_IRQC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config ST_IRQCHIP
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bool
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select REGMAP
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select MFD_SYSCON
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help
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Enables SysCfg Controlled IRQs on STi based platforms.
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config TANGO_IRQ
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config TS4800_IRQ
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tristate "TS-4800 IRQ controller"
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select IRQ_DOMAIN
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depends on HAS_IOMEM
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depends on SOC_IMX51 || COMPILE_TEST
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help
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Support for the TS-4800 FPGA IRQ controller
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on VERSATILE_FPGA_IRQ
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config XTENSA_MX
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config XILINX_INTC
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bool
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select IRQ_DOMAIN
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config IRQ_CROSSBAR
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bool
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help
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Support for a CROSSBAR ip that precedes the main interrupt controller.
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The primary irqchip invokes the crossbar's callback which inturn allocates
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a free irq and configures the IP. Thus the peripheral interrupts are
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routed to one of the free irqchip interrupt lines.
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config KEYSTONE_IRQ
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tristate "Keystone 2 IRQ controller IP"
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depends on ARCH_KEYSTONE
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help
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Support for Texas Instruments Keystone 2 IRQ controller IP which
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is part of the Keystone 2 IPC mechanism
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config MIPS_GIC
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bool
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select GENERIC_IRQ_IPI
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select IRQ_DOMAIN_HIERARCHY
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select MIPS_CM
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config INGENIC_IRQ
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bool
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depends on MACH_INGENIC
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default y
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config RENESAS_H8300H_INTC
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bool
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select IRQ_DOMAIN
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config RENESAS_H8S_INTC
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bool
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select IRQ_DOMAIN
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config IMX_GPCV2
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bool
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select IRQ_DOMAIN
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help
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Enables the wakeup IRQs for IMX platforms with GPCv2 block
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config IRQ_MXS
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def_bool y if MACH_ASM9260 || ARCH_MXS
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select IRQ_DOMAIN
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select STMP_DEVICE
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config MSCC_OCELOT_IRQ
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config MVEBU_GICP
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bool
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config MVEBU_ICU
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bool
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config MVEBU_ODMI
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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config MVEBU_PIC
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bool
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config MVEBU_SEI
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bool
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config LS_SCFG_MSI
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def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
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depends on PCI && PCI_MSI
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config PARTITION_PERCPU
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bool
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config EZNPS_GIC
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bool "NPS400 Global Interrupt Manager (GIM)"
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depends on ARC || (COMPILE_TEST && !64BIT)
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select IRQ_DOMAIN
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help
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Support the EZchip NPS400 global interrupt controller
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config STM32_EXTI
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config QCOM_IRQ_COMBINER
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bool "QCOM IRQ combiner support"
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depends on ARCH_QCOM && ACPI
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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help
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Say yes here to add support for the IRQ combiner devices embedded
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in Qualcomm Technologies chips.
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config IRQ_UNIPHIER_AIDET
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bool "UniPhier AIDET support" if COMPILE_TEST
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depends on ARCH_UNIPHIER || COMPILE_TEST
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default ARCH_UNIPHIER
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select IRQ_DOMAIN_HIERARCHY
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help
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Support for the UniPhier AIDET (ARM Interrupt Detector).
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config MESON_IRQ_GPIO
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bool "Meson GPIO Interrupt Multiplexer"
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depends on ARCH_MESON
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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help
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Support Meson SoC Family GPIO Interrupt Multiplexer
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config GOLDFISH_PIC
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bool "Goldfish programmable interrupt controller"
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depends on MIPS && (GOLDFISH || COMPILE_TEST)
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select IRQ_DOMAIN
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help
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Say yes here to enable Goldfish interrupt controller driver used
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for Goldfish based virtual platforms.
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config QCOM_PDC
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bool "QCOM PDC"
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depends on ARCH_QCOM
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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help
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Power Domain Controller driver to manage and configure wakeup
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IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
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config CSKY_MPINTC
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bool "C-SKY Multi Processor Interrupt Controller"
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depends on CSKY
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help
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Say yes here to enable C-SKY SMP interrupt controller driver used
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for C-SKY SMP system.
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In fact it's not mmio map in hw and it use ld/st to visit the
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controller's register inside CPU.
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config CSKY_APB_INTC
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bool "C-SKY APB Interrupt Controller"
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depends on CSKY
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help
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Say yes here to enable C-SKY APB interrupt controller driver used
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by C-SKY single core SOC system. It use mmio map apb-bus to visit
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the controller's register.
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config IMX_IRQSTEER
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bool "i.MX IRQSTEER support"
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depends on ARCH_MXC || COMPILE_TEST
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default ARCH_MXC
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select IRQ_DOMAIN
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help
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Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
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config LS1X_IRQ
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bool "Loongson-1 Interrupt Controller"
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depends on MACH_LOONGSON32
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default y
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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help
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Support for the Loongson-1 platform Interrupt Controller.
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endmenu
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config SIFIVE_PLIC
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bool "SiFive Platform-Level Interrupt Controller"
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depends on RISCV
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help
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This enables support for the PLIC chip found in SiFive (and
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potentially other) RISC-V systems. The PLIC controls devices
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interrupts and connects them to each core's local interrupt
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controller. Aside from timer and software interrupts, all other
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interrupt sources are subordinate to the PLIC.
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If you don't know what to do here, say Y.
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