mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 13:43:55 +08:00
8973aa4aec
Corrected the bits for power and iso.
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Fixes: f7225a83 ("clk: ns2: add clock support for Broadcom Northstar 2 SoC")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
289 lines
8.8 KiB
C
289 lines
8.8 KiB
C
/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/bcm-ns2.h>
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#include "clk-iproc.h"
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#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
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#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
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.pwr_shift = ps, .iso_shift = is }
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#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
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.p_reset_shift = prs }
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#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
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.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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.ka_width = kaw }
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#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
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#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
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.hold_shift = hs, .bypass_shift = bs }
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static const struct iproc_pll_ctrl genpll_scr = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
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.aon = AON_VAL(0x0, 1, 15, 12),
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.reset = RESET_VAL(0x4, 2, 1),
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.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
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.ndiv_int = REG_VAL(0x8, 4, 10),
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.pdiv = REG_VAL(0x8, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
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.status = REG_VAL(0x0, 27, 1),
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};
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static const struct iproc_clk_ctrl genpll_scr_clk[] = {
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/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
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* in NS2. However, it doesn't appear to be used anywhere, so setting
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* it to 0.
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*/
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[BCM_NS2_GENPLL_SCR_SCR_CLK] = {
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.channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 18, 12, 0),
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.mdiv = REG_VAL(0x18, 0, 8),
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},
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[BCM_NS2_GENPLL_SCR_FS_CLK] = {
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.channel = BCM_NS2_GENPLL_SCR_FS_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 19, 13, 0),
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.mdiv = REG_VAL(0x18, 8, 8),
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},
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[BCM_NS2_GENPLL_SCR_AUDIO_CLK] = {
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.channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 20, 14, 0),
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.mdiv = REG_VAL(0x14, 0, 8),
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},
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[BCM_NS2_GENPLL_SCR_CH3_UNUSED] = {
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.channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 21, 15, 0),
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.mdiv = REG_VAL(0x14, 8, 8),
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},
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[BCM_NS2_GENPLL_SCR_CH4_UNUSED] = {
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.channel = BCM_NS2_GENPLL_SCR_CH4_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 22, 16, 0),
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.mdiv = REG_VAL(0x14, 16, 8),
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},
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[BCM_NS2_GENPLL_SCR_CH5_UNUSED] = {
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.channel = BCM_NS2_GENPLL_SCR_CH5_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 23, 17, 0),
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.mdiv = REG_VAL(0x14, 24, 8),
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},
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};
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static void __init ns2_genpll_scr_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &genpll_scr, NULL, 0, genpll_scr_clk,
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ARRAY_SIZE(genpll_scr_clk));
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}
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CLK_OF_DECLARE(ns2_genpll_src_clk, "brcm,ns2-genpll-scr",
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ns2_genpll_scr_clk_init);
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static const struct iproc_pll_ctrl genpll_sw = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
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.aon = AON_VAL(0x0, 1, 11, 10),
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.reset = RESET_VAL(0x4, 2, 1),
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.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
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.ndiv_int = REG_VAL(0x8, 4, 10),
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.pdiv = REG_VAL(0x8, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
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.status = REG_VAL(0x0, 13, 1),
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};
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static const struct iproc_clk_ctrl genpll_sw_clk[] = {
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/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
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* in NS2. However, it doesn't appear to be used anywhere, so setting
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* it to 0.
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*/
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[BCM_NS2_GENPLL_SW_RPE_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_RPE_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 18, 12, 0),
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.mdiv = REG_VAL(0x18, 0, 8),
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},
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[BCM_NS2_GENPLL_SW_250_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_250_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 19, 13, 0),
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.mdiv = REG_VAL(0x18, 8, 8),
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},
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[BCM_NS2_GENPLL_SW_NIC_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_NIC_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 20, 14, 0),
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.mdiv = REG_VAL(0x14, 0, 8),
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},
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[BCM_NS2_GENPLL_SW_CHIMP_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_CHIMP_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 21, 15, 0),
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.mdiv = REG_VAL(0x14, 8, 8),
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},
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[BCM_NS2_GENPLL_SW_PORT_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_PORT_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 22, 16, 0),
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.mdiv = REG_VAL(0x14, 16, 8),
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},
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[BCM_NS2_GENPLL_SW_SDIO_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_SDIO_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 23, 17, 0),
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.mdiv = REG_VAL(0x14, 24, 8),
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},
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};
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static void __init ns2_genpll_sw_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &genpll_sw, NULL, 0, genpll_sw_clk,
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ARRAY_SIZE(genpll_sw_clk));
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}
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CLK_OF_DECLARE(ns2_genpll_sw_clk, "brcm,ns2-genpll-sw",
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ns2_genpll_sw_clk_init);
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static const struct iproc_pll_ctrl lcpll_ddr = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
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.aon = AON_VAL(0x0, 2, 1, 0),
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.reset = RESET_VAL(0x4, 2, 1),
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.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
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.ndiv_int = REG_VAL(0x8, 4, 10),
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.pdiv = REG_VAL(0x8, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
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.status = REG_VAL(0x0, 0, 1),
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};
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static const struct iproc_clk_ctrl lcpll_ddr_clk[] = {
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/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
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* in NS2. However, it doesn't appear to be used anywhere, so setting
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* it to 0.
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*/
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[BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK] = {
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.channel = BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 18, 12, 0),
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.mdiv = REG_VAL(0x14, 0, 8),
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},
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[BCM_NS2_LCPLL_DDR_DDR_CLK] = {
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.channel = BCM_NS2_LCPLL_DDR_DDR_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 19, 13, 0),
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.mdiv = REG_VAL(0x14, 8, 8),
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},
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[BCM_NS2_LCPLL_DDR_CH2_UNUSED] = {
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.channel = BCM_NS2_LCPLL_DDR_CH2_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 20, 14, 0),
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.mdiv = REG_VAL(0x10, 0, 8),
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},
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[BCM_NS2_LCPLL_DDR_CH3_UNUSED] = {
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.channel = BCM_NS2_LCPLL_DDR_CH3_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 21, 15, 0),
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.mdiv = REG_VAL(0x10, 8, 8),
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},
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[BCM_NS2_LCPLL_DDR_CH4_UNUSED] = {
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.channel = BCM_NS2_LCPLL_DDR_CH4_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 22, 16, 0),
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.mdiv = REG_VAL(0x10, 16, 8),
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},
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[BCM_NS2_LCPLL_DDR_CH5_UNUSED] = {
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.channel = BCM_NS2_LCPLL_DDR_CH5_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 23, 17, 0),
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.mdiv = REG_VAL(0x10, 24, 8),
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},
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};
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static void __init ns2_lcpll_ddr_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &lcpll_ddr, NULL, 0, lcpll_ddr_clk,
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ARRAY_SIZE(lcpll_ddr_clk));
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}
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CLK_OF_DECLARE(ns2_lcpll_ddr_clk, "brcm,ns2-lcpll-ddr",
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ns2_lcpll_ddr_clk_init);
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static const struct iproc_pll_ctrl lcpll_ports = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
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.aon = AON_VAL(0x0, 2, 5, 4),
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.reset = RESET_VAL(0x4, 2, 1),
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.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
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.ndiv_int = REG_VAL(0x8, 4, 10),
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.pdiv = REG_VAL(0x8, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
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.status = REG_VAL(0x0, 0, 1),
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};
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static const struct iproc_clk_ctrl lcpll_ports_clk[] = {
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/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
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* in NS2. However, it doesn't appear to be used anywhere, so setting
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* it to 0.
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*/
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[BCM_NS2_LCPLL_PORTS_WAN_CLK] = {
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.channel = BCM_NS2_LCPLL_PORTS_WAN_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 18, 12, 0),
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.mdiv = REG_VAL(0x14, 0, 8),
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},
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[BCM_NS2_LCPLL_PORTS_RGMII_CLK] = {
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.channel = BCM_NS2_LCPLL_PORTS_RGMII_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 19, 13, 0),
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.mdiv = REG_VAL(0x14, 8, 8),
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},
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[BCM_NS2_LCPLL_PORTS_CH2_UNUSED] = {
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.channel = BCM_NS2_LCPLL_PORTS_CH2_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 20, 14, 0),
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.mdiv = REG_VAL(0x10, 0, 8),
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},
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[BCM_NS2_LCPLL_PORTS_CH3_UNUSED] = {
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.channel = BCM_NS2_LCPLL_PORTS_CH3_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 21, 15, 0),
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.mdiv = REG_VAL(0x10, 8, 8),
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},
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[BCM_NS2_LCPLL_PORTS_CH4_UNUSED] = {
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.channel = BCM_NS2_LCPLL_PORTS_CH4_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 22, 16, 0),
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.mdiv = REG_VAL(0x10, 16, 8),
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},
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[BCM_NS2_LCPLL_PORTS_CH5_UNUSED] = {
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.channel = BCM_NS2_LCPLL_PORTS_CH5_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 23, 17, 0),
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.mdiv = REG_VAL(0x10, 24, 8),
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},
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};
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static void __init ns2_lcpll_ports_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &lcpll_ports, NULL, 0, lcpll_ports_clk,
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ARRAY_SIZE(lcpll_ports_clk));
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}
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CLK_OF_DECLARE(ns2_lcpll_ports_clk, "brcm,ns2-lcpll-ports",
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ns2_lcpll_ports_clk_init);
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