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59594e13e4
SMC, Static Memory Controller will need more accessors to fine configure its parameters. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
134 lines
3.5 KiB
C
134 lines
3.5 KiB
C
/*
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* linux/arch/arm/mach-at91/sam9_smc.c
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*
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* Copyright (C) 2008 Andrew Victor
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <mach/at91sam9_smc.h>
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#include "sam9_smc.h"
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#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
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static void __iomem *smc_base_addr[2];
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static void sam9_smc_cs_write_mode(void __iomem *base,
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struct sam9_smc_config *config)
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{
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__raw_writel(config->mode
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| AT91_SMC_TDF_(config->tdf_cycles),
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base + AT91_SMC_MODE);
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}
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void sam9_smc_write_mode(int id, int cs,
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struct sam9_smc_config *config)
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{
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sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
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}
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static void sam9_smc_cs_configure(void __iomem *base,
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struct sam9_smc_config *config)
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{
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/* Setup register */
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__raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
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| AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
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| AT91_SMC_NRDSETUP_(config->nrd_setup)
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| AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
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base + AT91_SMC_SETUP);
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/* Pulse register */
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__raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
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| AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
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| AT91_SMC_NRDPULSE_(config->nrd_pulse)
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| AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
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base + AT91_SMC_PULSE);
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/* Cycle register */
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__raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
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| AT91_SMC_NRDCYCLE_(config->read_cycle),
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base + AT91_SMC_CYCLE);
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/* Mode register */
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sam9_smc_cs_write_mode(base, config);
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}
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void sam9_smc_configure(int id, int cs,
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struct sam9_smc_config *config)
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{
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sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
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}
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static void sam9_smc_cs_read_mode(void __iomem *base,
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struct sam9_smc_config *config)
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{
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u32 val = __raw_readl(base + AT91_SMC_MODE);
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config->mode = (val & ~AT91_SMC_NWECYCLE);
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config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
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}
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void sam9_smc_read_mode(int id, int cs,
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struct sam9_smc_config *config)
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{
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sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
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}
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static void sam9_smc_cs_read(void __iomem *base,
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struct sam9_smc_config *config)
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{
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u32 val;
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/* Setup register */
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val = __raw_readl(base + AT91_SMC_SETUP);
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config->nwe_setup = val & AT91_SMC_NWESETUP;
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config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
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config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
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config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
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/* Pulse register */
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val = __raw_readl(base + AT91_SMC_PULSE);
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config->nwe_setup = val & AT91_SMC_NWEPULSE;
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config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
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config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
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config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
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/* Cycle register */
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val = __raw_readl(base + AT91_SMC_CYCLE);
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config->write_cycle = val & AT91_SMC_NWECYCLE;
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config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
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/* Mode register */
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sam9_smc_cs_read_mode(base, config);
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}
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void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
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{
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sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
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}
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void __init at91sam9_ioremap_smc(int id, u32 addr)
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{
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if (id > 1) {
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pr_warn("%s: id > 2\n", __func__);
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return;
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}
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smc_base_addr[id] = ioremap(addr, 512);
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if (!smc_base_addr[id])
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pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
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}
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