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21b30c00f3
Import bmips_5xxx_init.S from the stblinux-3.3 tree, and to make sure that this would work nicely with a BMIPS multiplatform kernel (with BMIPS330, BMIPS43XX and BMIPS5000 enabled), update soft_reset to check for the BMIPS5200 processor id (PRID_IMP_BMIPS5200) and execute bmips_5xxx_init for these processors to bring them online. Tested on 7425, 7429 and 7435 with CPU hotplug. 7435 SMP still needs some additional changes in the L1 interrupt area to work properly with interrupt affinity. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/12377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
323 lines
7.0 KiB
ArmAsm
323 lines
7.0 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
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*
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* Reset/NMI/re-entry vectors for BMIPS processors
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheops.h>
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#include <asm/cpu.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <asm/addrspace.h>
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#include <asm/hazards.h>
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#include <asm/bmips.h>
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.macro BARRIER
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.set mips32
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_ssnop
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_ssnop
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_ssnop
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.set mips0
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.endm
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/***********************************************************************
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* Alternate CPU1 startup vector for BMIPS4350
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*
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* On some systems the bootloader has already started CPU1 and configured
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* it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
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* triggered by the SW1 interrupt. If that is the case we try to move
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* it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
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***********************************************************************/
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LEAF(bmips_smp_movevec)
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la k0, 1f
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li k1, CKSEG1
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or k0, k1
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jr k0
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1:
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/* clear IV, pending IPIs */
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mtc0 zero, CP0_CAUSE
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/* re-enable IRQs to wait for SW1 */
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li k0, ST0_IE | ST0_BEV | STATUSF_IP1
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mtc0 k0, CP0_STATUS
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/* set up CPU1 CBR; move BASE to 0xa000_0000 */
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li k0, 0xff400000
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mtc0 k0, $22, 6
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/* set up relocation vector address based on thread ID */
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mfc0 k1, $22, 3
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srl k1, 16
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andi k1, 0x8000
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or k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
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or k0, k1
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li k1, 0xa0080000
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sw k1, 0(k0)
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/* wait here for SW1 interrupt from bmips_boot_secondary() */
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wait
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la k0, bmips_reset_nmi_vec
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li k1, CKSEG1
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or k0, k1
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jr k0
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END(bmips_smp_movevec)
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/***********************************************************************
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* Reset/NMI vector
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* For BMIPS processors that can relocate their exception vectors, this
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* entire function gets copied to 0x8000_0000.
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***********************************************************************/
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NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
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.set push
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.set noat
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.align 4
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#ifdef CONFIG_SMP
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/* if the NMI bit is clear, assume this is a CPU1 reset instead */
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li k1, (1 << 19)
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mfc0 k0, CP0_STATUS
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and k0, k1
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beqz k0, soft_reset
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#if defined(CONFIG_CPU_BMIPS5000)
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mfc0 k0, CP0_PRID
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li k1, PRID_IMP_BMIPS5000
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/* mask with PRID_IMP_BMIPS5000 to cover both variants */
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andi k0, PRID_IMP_BMIPS5000
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bne k0, k1, 1f
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/* if we're not on core 0, this must be the SMP boot signal */
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li k1, (3 << 25)
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mfc0 k0, $22
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and k0, k1
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bnez k0, bmips_smp_entry
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1:
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#endif /* CONFIG_CPU_BMIPS5000 */
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#endif /* CONFIG_SMP */
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/* nope, it's just a regular NMI */
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SAVE_ALL
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move a0, sp
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/* clear EXL, ERL, BEV so that TLB refills still work */
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mfc0 k0, CP0_STATUS
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li k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
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or k0, k1
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xor k0, k1
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mtc0 k0, CP0_STATUS
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BARRIER
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/* jump to the NMI handler function */
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la k0, nmi_handler
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jr k0
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RESTORE_ALL
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.set arch=r4000
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eret
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#ifdef CONFIG_SMP
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soft_reset:
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#if defined(CONFIG_CPU_BMIPS5000)
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mfc0 k0, CP0_PRID
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andi k0, 0xff00
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li k1, PRID_IMP_BMIPS5200
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bne k0, k1, bmips_smp_entry
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/* if running on TP 1, jump to bmips_smp_entry */
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mfc0 k0, $22
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li k1, (1 << 24)
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and k1, k0
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bnez k1, bmips_smp_entry
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nop
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/*
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* running on TP0, can not be core 0 (the boot core).
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* Check for soft reset. Indicates a warm boot
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*/
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mfc0 k0, $12
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li k1, (1 << 20)
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and k0, k1
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beqz k0, bmips_smp_entry
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/*
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* Warm boot.
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* Cache init is only done on TP0
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*/
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la k0, bmips_5xxx_init
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jalr k0
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nop
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b bmips_smp_entry
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nop
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#endif
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/***********************************************************************
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* CPU1 reset vector (used for the initial boot only)
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* This is still part of bmips_reset_nmi_vec().
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***********************************************************************/
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bmips_smp_entry:
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/* set up CP0 STATUS; enable FPU */
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li k0, 0x30000000
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mtc0 k0, CP0_STATUS
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BARRIER
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/* set local CP0 CONFIG to make kseg0 cacheable, write-back */
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mfc0 k0, CP0_CONFIG
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ori k0, 0x07
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xori k0, 0x04
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mtc0 k0, CP0_CONFIG
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mfc0 k0, CP0_PRID
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andi k0, 0xff00
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#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
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li k1, PRID_IMP_BMIPS43XX
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bne k0, k1, 2f
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/* initialize CPU1's local I-cache */
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li k0, 0x80000000
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li k1, 0x80010000
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mtc0 zero, $28
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mtc0 zero, $28, 1
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BARRIER
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1: cache Index_Store_Tag_I, 0(k0)
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addiu k0, 16
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bne k0, k1, 1b
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b 3f
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2:
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#endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
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#if defined(CONFIG_CPU_BMIPS5000)
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/* mask with PRID_IMP_BMIPS5000 to cover both variants */
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li k1, PRID_IMP_BMIPS5000
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andi k0, PRID_IMP_BMIPS5000
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bne k0, k1, 3f
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/* set exception vector base */
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la k0, ebase
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lw k0, 0(k0)
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mtc0 k0, $15, 1
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BARRIER
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#endif /* CONFIG_CPU_BMIPS5000 */
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3:
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/* jump back to kseg0 in case we need to remap the kseg1 area */
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la k0, 1f
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jr k0
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1:
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la k0, bmips_enable_xks01
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jalr k0
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/* use temporary stack to set up upper memory TLB */
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li sp, BMIPS_WARM_RESTART_VEC
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la k0, plat_wired_tlb_setup
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jalr k0
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/* switch to permanent stack and continue booting */
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.global bmips_secondary_reentry
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bmips_secondary_reentry:
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la k0, bmips_smp_boot_sp
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lw sp, 0(k0)
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la k0, bmips_smp_boot_gp
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lw gp, 0(k0)
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la k0, start_secondary
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jr k0
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#endif /* CONFIG_SMP */
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.align 4
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.global bmips_reset_nmi_vec_end
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bmips_reset_nmi_vec_end:
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END(bmips_reset_nmi_vec)
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.set pop
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/***********************************************************************
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* CPU1 warm restart vector (used for second and subsequent boots).
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* Also used for S2 standby recovery (PM).
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* This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
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***********************************************************************/
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LEAF(bmips_smp_int_vec)
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.align 4
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mfc0 k0, CP0_STATUS
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ori k0, 0x01
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xori k0, 0x01
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mtc0 k0, CP0_STATUS
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eret
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.align 4
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.global bmips_smp_int_vec_end
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bmips_smp_int_vec_end:
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END(bmips_smp_int_vec)
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/***********************************************************************
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* XKS01 support
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* Certain CPUs support extending kseg0 to 1024MB.
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***********************************************************************/
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LEAF(bmips_enable_xks01)
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#if defined(CONFIG_XKS01)
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mfc0 t0, CP0_PRID
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andi t2, t0, 0xff00
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#if defined(CONFIG_CPU_BMIPS4380)
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li t1, PRID_IMP_BMIPS43XX
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bne t2, t1, 1f
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andi t0, 0xff
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addiu t1, t0, -PRID_REV_BMIPS4380_HI
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bgtz t1, 2f
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addiu t0, -PRID_REV_BMIPS4380_LO
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bltz t0, 2f
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mfc0 t0, $22, 3
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li t1, 0x1ff0
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li t2, (1 << 12) | (1 << 9)
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or t0, t1
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xor t0, t1
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or t0, t2
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mtc0 t0, $22, 3
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BARRIER
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b 2f
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1:
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#endif /* CONFIG_CPU_BMIPS4380 */
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#if defined(CONFIG_CPU_BMIPS5000)
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li t1, PRID_IMP_BMIPS5000
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/* mask with PRID_IMP_BMIPS5000 to cover both variants */
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andi t2, PRID_IMP_BMIPS5000
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bne t2, t1, 2f
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mfc0 t0, $22, 5
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li t1, 0x01ff
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li t2, (1 << 8) | (1 << 5)
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or t0, t1
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xor t0, t1
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or t0, t2
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mtc0 t0, $22, 5
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BARRIER
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#endif /* CONFIG_CPU_BMIPS5000 */
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2:
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#endif /* defined(CONFIG_XKS01) */
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jr ra
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END(bmips_enable_xks01)
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