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9c3b443026
Unlike previous Allwinner SoCs, there is no central PHY control block on the A80. Also, OTG support is completely split off into a different controller. This adds a new driver to support the regular USB PHYs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
39 lines
1.2 KiB
Plaintext
39 lines
1.2 KiB
Plaintext
Allwinner sun9i USB PHY
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Required properties:
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- compatible : should be one of
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* allwinner,sun9i-a80-usb-phy
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- reg : a list of offset + length pairs
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- #phy-cells : from the generic phy bindings, must be 0
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- phy_type : "hsic" for HSIC usage;
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other values or absence of this property indicates normal USB
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- clocks : phandle + clock specifier for the phy clocks
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- clock-names : depending on the "phy_type" property,
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* "phy" for normal USB
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* "hsic_480M", "hsic_12M" for HSIC
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- resets : a list of phandle + reset specifier pairs
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- reset-names : depending on the "phy_type" property,
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* "phy" for normal USB
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* "hsic" for HSIC
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Optional Properties:
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- phy-supply : from the generic phy bindings, a phandle to a regulator that
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provides power to VBUS.
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It is recommended to list all clocks and resets available.
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The driver will only use those matching the phy_type.
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Example:
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usbphy1: phy@00a01800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a01800 0x4>;
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clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
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<&usb_phy_clk 3>;
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clock-names = "hsic_480M", "hsic_12M", "phy";
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resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
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reset-names = "hsic", "phy";
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status = "disabled";
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#phy-cells = <0>;
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};
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