mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 20:53:53 +08:00
0311c76e47
The displayport-phy is fully enclosed in the general register files (GRF). Therefore as seen from the device-tree it shouldn't be a separate platform- device but instead a sub-device of the GRF - using the simply-mfd mechanism. The driver entered the kernel in the current merge-window, so we can still adapt the binding without needing a fallback, as the binding hasn't been released with a full kernel yet. While the edp phy is fully part of the GRF, it doesn't have any separate register set there, so doesn't get any register-area assigned. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
27 lines
666 B
Plaintext
27 lines
666 B
Plaintext
Rockchip specific extensions to the Analogix Display Port PHY
|
|
------------------------------------
|
|
|
|
Required properties:
|
|
- compatible : should be one of the following supported values:
|
|
- "rockchip.rk3288-dp-phy"
|
|
- clocks: from common clock binding: handle to dp clock.
|
|
of memory mapped region.
|
|
- clock-names: from common clock binding:
|
|
Required elements: "24m"
|
|
- #phy-cells : from the generic PHY bindings, must be 0;
|
|
|
|
Example:
|
|
|
|
grf: syscon@ff770000 {
|
|
compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
|
|
|
|
...
|
|
|
|
edp_phy: edp-phy {
|
|
compatible = "rockchip,rk3288-dp-phy";
|
|
clocks = <&cru SCLK_EDP_24M>;
|
|
clock-names = "24m";
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|