Alexandre Ghiti 6d7f91d914 riscv: Get rid of CONFIG_PHYS_RAM_BASE in kernel physical address conversion ... The usage of CONFIG_PHYS_RAM_BASE for all kernel types was a mistake: this value is implementation-specific and this breaks the genericity of the RISC-V kernel. Fix this by introducing a new variable phys_ram_base that holds this value at runtime and use it in the kernel physical address conversion macro. Since this value is used only for XIP kernels, evaluate it only if CONFIG_XIP_KERNEL is set which in addition optimizes this macro for standard kernels at compile-time. Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> Tested-by: Emil Renner Berthing <kernel@esmil.dk> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Fixes: 44c9225729 ("RISC-V: enable XIP") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-08-06 22:41:28 -07:00
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cacheflush.c	mm: reorder includes after introduction of linux/pgtable.h	2020-06-09 09:39:13 -07:00
context.c	riscv: add ASID-based tlbflushing methods	2021-06-30 20:55:39 -07:00
extable.c	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
fault.c	riscv: Enable KFENCE for riscv64	2021-06-30 20:55:41 -07:00
hugetlbpage.c	hugetlbfs: remove hugetlb_add_hstate() warning for existing hstate	2020-06-03 20:09:46 -07:00
init.c	riscv: Get rid of CONFIG_PHYS_RAM_BASE in kernel physical address conversion	2021-08-06 22:41:28 -07:00
kasan_init.c	riscv: Ensure BPF_JIT_REGION_START aligned with PMD size	2021-06-18 21:10:05 -07:00
Makefile	riscv: Fixup patch_text panic in ftrace	2021-01-14 15:09:04 -08:00
pageattr.c	RISC-V Patches for the 5.11 Merge Window, Part 1	2020-12-18 10:43:07 -08:00
physaddr.c	riscv: Introduce structure that group all variables regarding kernel mapping	2021-07-05 18:04:00 -07:00
ptdump.c	riscv: Fix PTDUMP output now BPF region moved back to module region	2021-07-06 15:21:27 -07:00
tlbflush.c	riscv: add ASID-based tlbflushing methods	2021-06-30 20:55:39 -07:00