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0575b4b83e
Directives such as .long and .word do not magically cause the
assembler location counter to become aligned in gas. As a
result, using these directives in code sections can result in
misaligned data words when building a Thumb-2 kernel
(CONFIG_THUMB2_KERNEL).
This is a Bad Thing, since the ABI permits the compiler to
assume that fundamental types of word size or above are word-
aligned when accessing them from C. If the data is not really
word-aligned, this can cause impaired performance and stray
alignment faults in some circumstances.
In general, the following rules should be applied when using
data word declaration directives inside code sections:
* .quad and .double:
.align 3
* .long, .word, .single, .float:
.align (or .align 2)
* .short:
No explicit alignment required, since Thumb-2
instructions are always 2 or 4 bytes in size.
immediately after an instruction.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
LAKML-Reference: 1289913217-8672-1-git-send-email-dave.martin@linaro.org
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
137 lines
2.5 KiB
ArmAsm
137 lines
2.5 KiB
ArmAsm
/*
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* Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* r8 = bit 0-15: tx offset, bit 16-31: tx buffer size
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* r9 = bit 0-15: rx offset, bit 16-31: rx buffer size
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*/
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#define SSI_STX0 0x00
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#define SSI_SRX0 0x08
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#define SSI_SISR 0x14
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#define SSI_SIER 0x18
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#define SSI_SACNT 0x38
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#define SSI_SACNT_AC97EN (1 << 0)
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#define SSI_SIER_TFE0_EN (1 << 0)
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#define SSI_SISR_TFE0 (1 << 0)
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#define SSI_SISR_RFF0 (1 << 2)
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#define SSI_SIER_RFF0_EN (1 << 2)
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.text
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.global imx_ssi_fiq_start
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.global imx_ssi_fiq_end
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.global imx_ssi_fiq_base
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.global imx_ssi_fiq_rx_buffer
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.global imx_ssi_fiq_tx_buffer
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imx_ssi_fiq_start:
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ldr r12, imx_ssi_fiq_base
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/* TX */
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ldr r11, imx_ssi_fiq_tx_buffer
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/* shall we send? */
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ldr r13, [r12, #SSI_SIER]
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tst r13, #SSI_SIER_TFE0_EN
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beq 1f
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/* TX FIFO empty? */
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ldr r13, [r12, #SSI_SISR]
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tst r13, #SSI_SISR_TFE0
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beq 1f
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mov r10, #0x10000
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sub r10, #1
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and r10, r10, r8 /* r10: current buffer offset */
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add r11, r11, r10
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ldrh r13, [r11]
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strh r13, [r12, #SSI_STX0]
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ldrh r13, [r11, #2]
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strh r13, [r12, #SSI_STX0]
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ldrh r13, [r11, #4]
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strh r13, [r12, #SSI_STX0]
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ldrh r13, [r11, #6]
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strh r13, [r12, #SSI_STX0]
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add r10, #8
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lsr r13, r8, #16 /* r13: buffer size */
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cmp r10, r13
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lslgt r8, r13, #16
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addle r8, #8
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1:
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/* RX */
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/* shall we receive? */
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ldr r13, [r12, #SSI_SIER]
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tst r13, #SSI_SIER_RFF0_EN
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beq 1f
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/* RX FIFO full? */
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ldr r13, [r12, #SSI_SISR]
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tst r13, #SSI_SISR_RFF0
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beq 1f
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ldr r11, imx_ssi_fiq_rx_buffer
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mov r10, #0x10000
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sub r10, #1
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and r10, r10, r9 /* r10: current buffer offset */
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add r11, r11, r10
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ldr r13, [r12, #SSI_SACNT]
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tst r13, #SSI_SACNT_AC97EN
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ldr r13, [r12, #SSI_SRX0]
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strh r13, [r11]
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ldr r13, [r12, #SSI_SRX0]
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strh r13, [r11, #2]
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/* dummy read to skip slot 12 */
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ldrne r13, [r12, #SSI_SRX0]
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ldr r13, [r12, #SSI_SRX0]
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strh r13, [r11, #4]
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ldr r13, [r12, #SSI_SRX0]
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strh r13, [r11, #6]
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/* dummy read to skip slot 12 */
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ldrne r13, [r12, #SSI_SRX0]
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add r10, #8
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lsr r13, r9, #16 /* r13: buffer size */
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cmp r10, r13
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lslgt r9, r13, #16
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addle r9, #8
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1:
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@ return from FIQ
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subs pc, lr, #4
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.align
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imx_ssi_fiq_base:
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.word 0x0
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imx_ssi_fiq_rx_buffer:
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.word 0x0
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imx_ssi_fiq_tx_buffer:
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.word 0x0
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imx_ssi_fiq_end:
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