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ca5ed2f5c7
"extern inline" doesn't make much sense. Signed-off-by: Adrian Bunk <bunk@stusta.de> Cc: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
251 lines
7.1 KiB
C
251 lines
7.1 KiB
C
#ifndef __ASM_SH64_IO_H
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#define __ASM_SH64_IO_H
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* include/asm-sh64/io.h
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003 Paul Mundt
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*
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*/
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/*
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* Convention:
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* read{b,w,l}/write{b,w,l} are for PCI,
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* while in{b,w,l}/out{b,w,l} are for ISA
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* These may (will) be platform specific function.
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*
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* In addition, we have
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* ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
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* which are processor specific. Address should be the result of
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* onchip_remap();
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*/
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#include <linux/compiler.h>
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#include <asm/cache.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm-generic/iomap.h>
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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#define page_to_bus page_to_phys
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/*
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* Nothing overly special here.. instead of doing the same thing
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* over and over again, we just define a set of sh64_in/out functions
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* with an implicit size. The traditional read{b,w,l}/write{b,w,l}
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* mess is wrapped to this, as are the SH-specific ctrl_in/out routines.
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*/
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static inline unsigned char sh64_in8(const volatile void __iomem *addr)
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{
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return *(volatile unsigned char __force *)addr;
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}
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static inline unsigned short sh64_in16(const volatile void __iomem *addr)
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{
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return *(volatile unsigned short __force *)addr;
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}
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static inline unsigned int sh64_in32(const volatile void __iomem *addr)
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{
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return *(volatile unsigned int __force *)addr;
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}
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static inline unsigned long long sh64_in64(const volatile void __iomem *addr)
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{
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return *(volatile unsigned long long __force *)addr;
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}
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static inline void sh64_out8(unsigned char b, volatile void __iomem *addr)
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{
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*(volatile unsigned char __force *)addr = b;
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wmb();
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}
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static inline void sh64_out16(unsigned short b, volatile void __iomem *addr)
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{
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*(volatile unsigned short __force *)addr = b;
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wmb();
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}
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static inline void sh64_out32(unsigned int b, volatile void __iomem *addr)
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{
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*(volatile unsigned int __force *)addr = b;
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wmb();
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}
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static inline void sh64_out64(unsigned long long b, volatile void __iomem *addr)
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{
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*(volatile unsigned long long __force *)addr = b;
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wmb();
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}
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#define readb(addr) sh64_in8(addr)
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#define readw(addr) sh64_in16(addr)
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#define readl(addr) sh64_in32(addr)
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#define readb_relaxed(addr) sh64_in8(addr)
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#define readw_relaxed(addr) sh64_in16(addr)
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#define readl_relaxed(addr) sh64_in32(addr)
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#define writeb(b, addr) sh64_out8(b, addr)
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#define writew(b, addr) sh64_out16(b, addr)
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#define writel(b, addr) sh64_out32(b, addr)
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#define ctrl_inb(addr) sh64_in8(ioport_map(addr, 1))
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#define ctrl_inw(addr) sh64_in16(ioport_map(addr, 2))
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#define ctrl_inl(addr) sh64_in32(ioport_map(addr, 4))
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#define ctrl_outb(b, addr) sh64_out8(b, ioport_map(addr, 1))
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#define ctrl_outw(b, addr) sh64_out16(b, ioport_map(addr, 2))
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#define ctrl_outl(b, addr) sh64_out32(b, ioport_map(addr, 4))
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#define ioread8(addr) sh64_in8(addr)
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#define ioread16(addr) sh64_in16(addr)
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#define ioread32(addr) sh64_in32(addr)
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#define iowrite8(b, addr) sh64_out8(b, addr)
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#define iowrite16(b, addr) sh64_out16(b, addr)
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#define iowrite32(b, addr) sh64_out32(b, addr)
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#define inb(addr) ctrl_inb(addr)
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#define inw(addr) ctrl_inw(addr)
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#define inl(addr) ctrl_inl(addr)
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#define outb(b, addr) ctrl_outb(b, addr)
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#define outw(b, addr) ctrl_outw(b, addr)
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#define outl(b, addr) ctrl_outl(b, addr)
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void outsw(unsigned long port, const void *addr, unsigned long count);
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void insw(unsigned long port, void *addr, unsigned long count);
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void outsl(unsigned long port, const void *addr, unsigned long count);
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void insl(unsigned long port, void *addr, unsigned long count);
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void memcpy_toio(void __iomem *to, const void *from, long count);
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void memcpy_fromio(void *to, void __iomem *from, long count);
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#define mmiowb()
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#ifdef __KERNEL__
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#ifdef CONFIG_SH_CAYMAN
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extern unsigned long smsc_superio_virt;
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#endif
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#ifdef CONFIG_PCI
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extern unsigned long pciio_virt;
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#endif
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* Change virtual addresses to physical addresses and vv.
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* These are trivial on the 1:1 Linux/SuperH mapping
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*/
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static inline unsigned long virt_to_phys(volatile void * address)
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{
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return __pa(address);
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}
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static inline void * phys_to_virt(unsigned long address)
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{
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return __va(address);
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}
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extern void * __ioremap(unsigned long phys_addr, unsigned long size,
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unsigned long flags);
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static inline void * ioremap(unsigned long phys_addr, unsigned long size)
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{
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return __ioremap(phys_addr, size, 1);
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}
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static inline void * ioremap_nocache (unsigned long phys_addr, unsigned long size)
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{
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return __ioremap(phys_addr, size, 0);
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}
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extern void iounmap(void *addr);
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unsigned long onchip_remap(unsigned long addr, unsigned long size, const char* name);
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extern void onchip_unmap(unsigned long vaddr);
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static __inline__ int check_signature(volatile void __iomem *io_addr,
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const unsigned char *signature, int length)
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{
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int retval = 0;
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do {
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if (readb(io_addr) != *signature)
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goto out;
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io_addr++;
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signature++;
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length--;
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} while (length);
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retval = 1;
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out:
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return retval;
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}
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/*
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* The caches on some architectures aren't dma-coherent and have need to
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* handle this in software. There are three types of operations that
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* can be applied to dma buffers.
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*
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* - dma_cache_wback_inv(start, size) makes caches and RAM coherent by
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* writing the content of the caches back to memory, if necessary.
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* The function also invalidates the affected part of the caches as
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* necessary before DMA transfers from outside to memory.
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* - dma_cache_inv(start, size) invalidates the affected parts of the
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* caches. Dirty lines of the caches may be written back or simply
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* be discarded. This operation is necessary before dma operations
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* to the memory.
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* - dma_cache_wback(start, size) writes back any dirty lines but does
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* not invalidate the cache. This can be used before DMA reads from
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* memory,
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*/
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static __inline__ void dma_cache_wback_inv (unsigned long start, unsigned long size)
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{
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unsigned long s = start & L1_CACHE_ALIGN_MASK;
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unsigned long e = (start + size) & L1_CACHE_ALIGN_MASK;
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for (; s <= e; s += L1_CACHE_BYTES)
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asm volatile ("ocbp %0, 0" : : "r" (s));
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}
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static __inline__ void dma_cache_inv (unsigned long start, unsigned long size)
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{
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// Note that caller has to be careful with overzealous
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// invalidation should there be partial cache lines at the extremities
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// of the specified range
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unsigned long s = start & L1_CACHE_ALIGN_MASK;
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unsigned long e = (start + size) & L1_CACHE_ALIGN_MASK;
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for (; s <= e; s += L1_CACHE_BYTES)
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asm volatile ("ocbi %0, 0" : : "r" (s));
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}
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static __inline__ void dma_cache_wback (unsigned long start, unsigned long size)
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{
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unsigned long s = start & L1_CACHE_ALIGN_MASK;
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unsigned long e = (start + size) & L1_CACHE_ALIGN_MASK;
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for (; s <= e; s += L1_CACHE_BYTES)
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asm volatile ("ocbwb %0, 0" : : "r" (s));
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}
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH64_IO_H */
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