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6d0c8c723f
Exynos7 supports 3 MMC channels, add the MMC gate clocks to support them. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
82 lines
1.8 KiB
C
82 lines
1.8 KiB
C
/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
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#define _DT_BINDINGS_CLOCK_EXYNOS7_H
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/* TOPC */
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#define DOUT_ACLK_PERIS 1
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#define DOUT_SCLK_BUS0_PLL 2
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#define DOUT_SCLK_BUS1_PLL 3
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#define DOUT_SCLK_CC_PLL 4
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#define DOUT_SCLK_MFC_PLL 5
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#define TOPC_NR_CLK 6
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/* TOP0 */
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#define DOUT_ACLK_PERIC1 1
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#define DOUT_ACLK_PERIC0 2
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#define CLK_SCLK_UART0 3
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#define CLK_SCLK_UART1 4
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#define CLK_SCLK_UART2 5
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#define CLK_SCLK_UART3 6
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#define TOP0_NR_CLK 7
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/* TOP1 */
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#define DOUT_ACLK_FSYS1_200 1
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#define DOUT_ACLK_FSYS0_200 2
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#define DOUT_SCLK_MMC2 3
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#define DOUT_SCLK_MMC1 4
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#define DOUT_SCLK_MMC0 5
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#define CLK_SCLK_MMC2 6
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#define CLK_SCLK_MMC1 7
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#define CLK_SCLK_MMC0 8
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#define TOP1_NR_CLK 9
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/* PERIC0 */
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#define PCLK_UART0 1
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#define SCLK_UART0 2
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#define PCLK_HSI2C0 3
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#define PCLK_HSI2C1 4
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#define PCLK_HSI2C4 5
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#define PCLK_HSI2C5 6
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#define PCLK_HSI2C9 7
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#define PCLK_HSI2C10 8
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#define PCLK_HSI2C11 9
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#define PERIC0_NR_CLK 10
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/* PERIC1 */
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#define PCLK_UART1 1
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#define PCLK_UART2 2
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#define PCLK_UART3 3
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#define SCLK_UART1 4
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#define SCLK_UART2 5
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#define SCLK_UART3 6
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#define PCLK_HSI2C2 7
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#define PCLK_HSI2C3 8
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#define PCLK_HSI2C6 9
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#define PCLK_HSI2C7 10
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#define PCLK_HSI2C8 11
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#define PERIC1_NR_CLK 12
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/* PERIS */
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#define PCLK_CHIPID 1
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#define SCLK_CHIPID 2
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#define PERIS_NR_CLK 3
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/* FSYS0 */
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#define ACLK_MMC2 1
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#define FSYS0_NR_CLK 2
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/* FSYS1 */
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#define ACLK_MMC1 1
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#define ACLK_MMC0 2
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#define FSYS1_NR_CLK 3
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
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