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There are some new broken doc links due to yaml renames at DT. Developers should really run: ./scripts/documentation-file-ref-check in order to solve those issues while submitting patches. This tool can even fix most of the issues with: ./scripts/documentation-file-ref-check --fix Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/0e4a7f0b7efcc8109c8a41a2e13c8adde4d9c6b9.1592203542.git.mchehab+huawei@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
72 lines
2.9 KiB
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72 lines
2.9 KiB
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.. SPDX-License-Identifier: GPL-2.0
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===============================================
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Ingenic JZ47xx SoCs Timer/Counter Unit hardware
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===============================================
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The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
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hardware block. It features up to to eight channels, that can be used as
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counters, timers, or PWM.
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- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
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have eight channels.
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- JZ4725B introduced a separate channel, called Operating System Timer
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(OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
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64-bit.
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- Each one of the TCU channels has its own clock, which can be reparented to three
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different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
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- The watchdog and OST hardware blocks also feature a TCSR register with the same
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format in their register space.
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- The TCU registers used to gate/ungate can also gate/ungate the watchdog and
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OST clocks.
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- Each TCU channel works in one of two modes:
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- mode TCU1: channels cannot work in sleep mode, but are easier to
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operate.
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- mode TCU2: channels can work in sleep mode, but the operation is a bit
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more complicated than with TCU1 channels.
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- The mode of each TCU channel depends on the SoC used:
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- On the oldest SoCs (up to JZ4740), all of the eight channels operate in
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TCU1 mode.
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- On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
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- On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
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others operate as TCU1.
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- Each channel can generate an interrupt. Some channels share an interrupt
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line, some don't, and this changes between SoC versions:
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- on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
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own interrupt line; channels 2-7 share the last interrupt line.
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- On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
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interrupt line; the OST uses the last interrupt line.
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- on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
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channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
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the OST uses the last interrupt line.
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Implementation
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==============
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The functionalities of the TCU hardware are spread across multiple drivers:
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=========== =====
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clocks drivers/clk/ingenic/tcu.c
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interrupts drivers/irqchip/irq-ingenic-tcu.c
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timers drivers/clocksource/ingenic-timer.c
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OST drivers/clocksource/ingenic-ost.c
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PWM drivers/pwm/pwm-jz4740.c
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watchdog drivers/watchdog/jz4740_wdt.c
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=========== =====
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Because various functionalities of the TCU that belong to different drivers
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and frameworks can be controlled from the same registers, all of these
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drivers access their registers through the same regmap.
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For more information regarding the devicetree bindings of the TCU drivers,
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have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml.
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