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819a88263d
ARM64 CPU operations such as cpu_init and cpu_init_idle take a struct device_node pointer as a parameter, which corresponds to the device tree node of the logical cpu on which the operation has to be applied. With the advent of ACPI on arm64, where MADT static table entries are used to initialize cpus, the device tree node parameter in cpu_ops hooks become useless when booting with ACPI, since in that case cpu device tree nodes are not present and can not be used for cpu initialization. The current cpu_init hook requires a struct device_node pointer parameter because it is called while parsing the device tree to initialize CPUs, when the cpu_logical_map (that is used to match a cpu node reg property to a device tree node) for a given logical cpu id is not set up yet. This means that the cpu_init hook cannot rely on the of_get_cpu_node function to retrieve the device tree node corresponding to the logical cpu id passed in as parameter, so the cpu device tree node must be passed in as a parameter to fix this catch-22 dependency cycle. This patch reshuffles the cpu_logical_map initialization code so that the cpu_init cpu_ops hook can safely use the of_get_cpu_node function to retrieve the cpu device tree node, removing the need for the device tree node pointer parameter. In the process, the patch removes device tree node parameters from all cpu_ops hooks, in preparation for SMP DT/ACPI cpus initialization consolidation. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Hanjun Guo <hanjun.guo@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Hanjun Guo <hanjun.guo@linaro.org> Tested-by: Mark Rutland <mark.rutland@arm.com> [DT] Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
134 lines
3.3 KiB
C
134 lines
3.3 KiB
C
/*
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* Spin Table SMP initialisation
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*
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* Copyright (C) 2013 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/cacheflush.h>
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#include <asm/cpu_ops.h>
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#include <asm/cputype.h>
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#include <asm/io.h>
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#include <asm/smp_plat.h>
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extern void secondary_holding_pen(void);
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volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
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static phys_addr_t cpu_release_addr[NR_CPUS];
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/*
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* Write secondary_holding_pen_release in a way that is guaranteed to be
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* visible to all observers, irrespective of whether they're taking part
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* in coherency or not. This is necessary for the hotplug code to work
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* reliably.
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*/
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static void write_pen_release(u64 val)
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{
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void *start = (void *)&secondary_holding_pen_release;
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unsigned long size = sizeof(secondary_holding_pen_release);
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secondary_holding_pen_release = val;
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__flush_dcache_area(start, size);
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}
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static int smp_spin_table_cpu_init(unsigned int cpu)
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{
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struct device_node *dn;
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dn = of_get_cpu_node(cpu, NULL);
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if (!dn)
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return -ENODEV;
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/*
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* Determine the address from which the CPU is polling.
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*/
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if (of_property_read_u64(dn, "cpu-release-addr",
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&cpu_release_addr[cpu])) {
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pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
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cpu);
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return -1;
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}
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return 0;
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}
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static int smp_spin_table_cpu_prepare(unsigned int cpu)
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{
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__le64 __iomem *release_addr;
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if (!cpu_release_addr[cpu])
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return -ENODEV;
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/*
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* The cpu-release-addr may or may not be inside the linear mapping.
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* As ioremap_cache will either give us a new mapping or reuse the
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* existing linear mapping, we can use it to cover both cases. In
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* either case the memory will be MT_NORMAL.
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*/
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release_addr = ioremap_cache(cpu_release_addr[cpu],
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sizeof(*release_addr));
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if (!release_addr)
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return -ENOMEM;
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/*
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* We write the release address as LE regardless of the native
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* endianess of the kernel. Therefore, any boot-loaders that
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* read this address need to convert this address to the
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* boot-loader's endianess before jumping. This is mandated by
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* the boot protocol.
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*/
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writeq_relaxed(__pa(secondary_holding_pen), release_addr);
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__flush_dcache_area((__force void *)release_addr,
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sizeof(*release_addr));
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/*
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* Send an event to wake up the secondary CPU.
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*/
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sev();
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iounmap(release_addr);
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return 0;
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}
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static int smp_spin_table_cpu_boot(unsigned int cpu)
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{
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/*
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* Update the pen release flag.
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*/
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write_pen_release(cpu_logical_map(cpu));
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/*
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* Send an event, causing the secondaries to read pen_release.
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*/
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sev();
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return 0;
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}
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const struct cpu_operations smp_spin_table_ops = {
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.name = "spin-table",
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.cpu_init = smp_spin_table_cpu_init,
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.cpu_prepare = smp_spin_table_cpu_prepare,
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.cpu_boot = smp_spin_table_cpu_boot,
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};
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