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15e28bf130
This driver adds /dev/watchdog support for the AMD sp5100 aka SB7x0 chipsets. It follows the same conventions found in other /dev/watchdog drivers. Signed-off-by: Priyanka Gupta <priyankag@google.com> Signed-off-by: Mike Waychison <mikew@google.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
42 lines
1.1 KiB
C
42 lines
1.1 KiB
C
/*
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* sp5100_tco: TCO timer driver for sp5100 chipsets.
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*
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* (c) Copyright 2009 Google Inc., All Rights Reserved.
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*
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* TCO timer driver for sp5100 chipsets
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*/
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/*
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* Some address definitions for the Watchdog
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*/
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#define SP5100_WDT_MEM_MAP_SIZE 0x08
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#define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
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#define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
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#define SP5100_WDT_START_STOP_BIT 1
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#define SP5100_WDT_TRIGGER_BIT (1 << 7)
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#define SP5100_PCI_WATCHDOG_MISC_REG 0x41
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#define SP5100_PCI_WATCHDOG_DECODE_EN (1 << 3)
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#define SP5100_PM_IOPORTS_SIZE 0x02
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/* These two IO registers are hardcoded and there doesn't seem to be a way to
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* read them from a register.
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*/
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#define SP5100_IO_PM_INDEX_REG 0xCD6
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#define SP5100_IO_PM_DATA_REG 0xCD7
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#define SP5100_PM_WATCHDOG_CONTROL 0x69
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#define SP5100_PM_WATCHDOG_BASE0 0x6C
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#define SP5100_PM_WATCHDOG_BASE1 0x6D
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#define SP5100_PM_WATCHDOG_BASE2 0x6E
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#define SP5100_PM_WATCHDOG_BASE3 0x6F
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#define SP5100_PM_WATCHDOG_FIRED (1 << 1)
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#define SP5100_PM_WATCHDOG_ACTION_RESET (1 << 2)
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#define SP5100_PM_WATCHDOG_DISABLE 1
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#define SP5100_PM_WATCHDOG_SECOND_RES (3 << 1)
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