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1bebd72a71
Add r8a7791 CMT support via channel 0 of CMT0. At this point the CMT is used for clock event operation, but in the future the arch timer will be the main timer and the CMT will be used for deep sleep wake up only. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> (cherry picked from commit a7663b88280d00359715817620798e99d54d401c) Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
238 lines
7.1 KiB
C
238 lines
7.1 KiB
C
/*
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* r8a7791 clock framework support
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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#include <mach/common.h>
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/*
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* MD EXTAL PLL0 PLL1 PLL3
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* 14 13 19 (MHz) *1 *1
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*---------------------------------------------------
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* 0 0 0 15 x 1 x172/2 x208/2 x106
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* 0 0 1 15 x 1 x172/2 x208/2 x88
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* 0 1 0 20 x 1 x130/2 x156/2 x80
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* 0 1 1 20 x 1 x130/2 x156/2 x66
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* 1 0 0 26 / 2 x200/2 x240/2 x122
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* 1 0 1 26 / 2 x200/2 x240/2 x102
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* 1 1 0 30 / 2 x172/2 x208/2 x106
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* 1 1 1 30 / 2 x172/2 x208/2 x88
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*
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* *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
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* see "p1 / 2" on R8A7791_CLOCK_ROOT() below
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*/
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#define MD(nr) (1 << nr)
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#define CPG_BASE 0xe6150000
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#define CPG_LEN 0x1000
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#define SMSTPCR0 0xE6150130
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#define SMSTPCR1 0xE6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xE615013C
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#define SMSTPCR5 0xE6150144
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#define SMSTPCR7 0xe615014c
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#define SMSTPCR8 0xE6150990
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#define SMSTPCR9 0xE6150994
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#define SMSTPCR10 0xE6150998
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#define SMSTPCR11 0xE615099C
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#define MODEMR 0xE6160060
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#define SDCKCR 0xE6150074
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#define SD2CKCR 0xE6150078
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#define SD3CKCR 0xE615007C
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#define MMC0CKCR 0xE6150240
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#define MMC1CKCR 0xE6150244
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#define SSPCKCR 0xE6150248
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#define SSPRSCKCR 0xE615024C
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static struct clk_mapping cpg_mapping = {
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.phys = CPG_BASE,
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.len = CPG_LEN,
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};
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static struct clk extal_clk = {
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/* .rate will be updated on r8a7791_clock_init() */
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.mapping = &cpg_mapping,
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};
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static struct sh_clk_ops followparent_clk_ops = {
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.recalc = followparent_recalc,
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};
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static struct clk main_clk = {
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/* .parent will be set r8a73a4_clock_init */
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.ops = &followparent_clk_ops,
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};
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/*
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* clock ratio of these clock will be updated
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* on r8a7791_clock_init()
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*/
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SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
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/* fixed ratio clock */
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SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
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SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
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SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
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SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
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SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
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SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
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SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
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static struct clk *main_clks[] = {
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&extal_clk,
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&extal_div2_clk,
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&main_clk,
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&pll1_clk,
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&pll1_div2_clk,
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&pll3_clk,
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&hp_clk,
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&p_clk,
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&rclk_clk,
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&mp_clk,
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&cp_clk,
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};
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/* MSTP */
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enum {
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MSTP721, MSTP720,
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MSTP719, MSTP718, MSTP715, MSTP714,
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MSTP216, MSTP207, MSTP206,
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MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
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MSTP124,
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MSTP_NR
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};
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
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[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
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[MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
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[MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
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[MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
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[MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
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[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
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[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
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[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
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[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
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[MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */
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[MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */
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[MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */
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[MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
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CLKDEV_CON_ID("main", &main_clk),
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CLKDEV_CON_ID("pll1", &pll1_clk),
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CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
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CLKDEV_CON_ID("pll3", &pll3_clk),
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CLKDEV_CON_ID("hp", &hp_clk),
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CLKDEV_CON_ID("p", &p_clk),
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CLKDEV_CON_ID("rclk", &rclk_clk),
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CLKDEV_CON_ID("mp", &mp_clk),
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CLKDEV_CON_ID("cp", &cp_clk),
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CLKDEV_CON_ID("peripheral_clk", &hp_clk),
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/* MSTP */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */
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CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */
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CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */
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CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */
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CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */
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CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */
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CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
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CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
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CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
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CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
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};
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#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
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extal_clk.rate = e * 1000 * 1000; \
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main_clk.parent = m; \
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SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
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if (mode & MD(19)) \
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SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
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else \
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SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
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void __init r8a7791_clock_init(void)
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{
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void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
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u32 mode;
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int k, ret = 0;
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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switch (mode & (MD(14) | MD(13))) {
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case 0:
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R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
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break;
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case MD(13):
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R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
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break;
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case MD(14):
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R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
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break;
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case MD(13) | MD(14):
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R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
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break;
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}
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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shmobile_clk_init();
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else
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goto epanic;
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return;
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epanic:
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panic("failed to setup r8a7791 clocks\n");
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}
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