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6c16dedfd4
Exynos5420 is octa-core SoC from Samsung. Hence extend exynos-mct clocksource driver to support 8 local interrupts. Also extend dts entries for 8 interrupts. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
378 lines
8.2 KiB
Plaintext
378 lines
8.2 KiB
Plaintext
/*
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* SAMSUNG EXYNOS5420 SoC device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
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* EXYNOS5420 based board files can include this file and provide
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* values for board specfic bindings.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos5.dtsi"
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#include "exynos5420-pinctrl.dtsi"
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#include <dt-bindings/clk/exynos-audss-clk.h>
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/ {
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compatible = "samsung,exynos5420";
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aliases {
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mshc0 = &mmc_0;
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mshc1 = &mmc_1;
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mshc2 = &mmc_2;
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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pinctrl4 = &pinctrl_4;
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i2c0 = &i2c_0;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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gsc0 = &gsc_0;
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gsc1 = &gsc_1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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};
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};
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5420-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5420-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&clock 148>;
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clock-names = "sclk_audio";
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};
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codec@11000000 {
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compatible = "samsung,mfc-v7";
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reg = <0x11000000 0x10000>;
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interrupts = <0 96 0>;
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clocks = <&clock 401>;
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clock-names = "mfc";
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};
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mmc_0: mmc@12200000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <0 75 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12200000 0x2000>;
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clocks = <&clock 351>, <&clock 132>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_1: mmc@12210000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <0 76 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12210000 0x2000>;
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clocks = <&clock 352>, <&clock 133>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_2: mmc@12220000 {
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compatible = "samsung,exynos5420-dw-mshc";
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interrupts = <0 77 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12220000 0x1000>;
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clocks = <&clock 353>, <&clock 134>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mct@101C0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0x800>;
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interrupt-controller;
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#interrups-cells = <1>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
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<8>, <9>, <10>, <11>;
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clocks = <&clock 1>, <&clock 315>;
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clock-names = "fin_pll", "mct";
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &combiner 23 3>,
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<1 &combiner 23 4>,
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<2 &combiner 25 2>,
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<3 &combiner 25 3>,
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<4 &gic 0 120 0>,
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<5 &gic 0 121 0>,
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<6 &gic 0 122 0>,
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<7 &gic 0 123 0>,
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<8 &gic 0 128 0>,
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<9 &gic 0 129 0>,
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<10 &gic 0 130 0>,
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<11 &gic 0 131 0>;
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};
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};
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gsc_pd: power-domain@10044000 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044000 0x20>;
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};
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isp_pd: power-domain@10044020 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044020 0x20>;
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};
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mfc_pd: power-domain@10044060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044060 0x20>;
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};
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disp_pd: power-domain@100440C0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440C0 0x20>;
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};
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mau_pd: power-domain@100440E0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440E0 0x20>;
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};
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g2d_pd: power-domain@10044100 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044100 0x20>;
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};
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msc_pd: power-domain@10044120 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044120 0x20>;
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};
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pinctrl_0: pinctrl@13400000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13400000 0x1000>;
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interrupts = <0 45 0>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 32 0>;
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};
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};
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pinctrl_1: pinctrl@13410000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13410000 0x1000>;
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interrupts = <0 78 0>;
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};
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pinctrl_2: pinctrl@14000000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14000000 0x1000>;
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interrupts = <0 46 0>;
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};
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pinctrl_3: pinctrl@14010000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14010000 0x1000>;
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interrupts = <0 50 0>;
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};
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pinctrl_4: pinctrl@03860000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupts = <0 47 0>;
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};
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rtc@101E0000 {
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clocks = <&clock 317>;
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clock-names = "rtc";
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status = "okay";
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};
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serial@12C00000 {
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clocks = <&clock 257>, <&clock 128>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial@12C10000 {
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clocks = <&clock 258>, <&clock 129>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial@12C20000 {
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clocks = <&clock 259>, <&clock 130>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial@12C30000 {
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clocks = <&clock 260>, <&clock 131>;
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clock-names = "uart", "clk_uart_baud0";
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};
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dp_phy: video-phy@10040728 {
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compatible = "samsung,exynos5250-dp-video-phy";
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reg = <0x10040728 4>;
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#phy-cells = <0>;
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};
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dp-controller@145B0000 {
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clocks = <&clock 412>;
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clock-names = "dp";
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phys = <&dp_phy>;
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phy-names = "dp";
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};
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fimd@14400000 {
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samsung,power-domain = <&disp_pd>;
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clocks = <&clock 147>, <&clock 421>;
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clock-names = "sclk_fimd", "fimd";
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};
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adc: adc@12D10000 {
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compatible = "samsung,exynos-adc-v2";
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reg = <0x12D10000 0x100>, <0x10040720 0x4>;
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interrupts = <0 106 0>;
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clocks = <&clock 270>;
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clock-names = "adc";
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#io-channel-cells = <1>;
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io-channel-ranges;
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status = "disabled";
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};
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i2c_0: i2c@12C60000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C60000 0x100>;
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interrupts = <0 56 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock 261>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_bus>;
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status = "disabled";
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};
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i2c_1: i2c@12C70000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C70000 0x100>;
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interrupts = <0 57 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock 262>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_bus>;
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status = "disabled";
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};
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i2c_2: i2c@12C80000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C80000 0x100>;
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interrupts = <0 58 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock 263>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_bus>;
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status = "disabled";
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};
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i2c_3: i2c@12C90000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C90000 0x100>;
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interrupts = <0 59 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock 264>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_bus>;
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status = "disabled";
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};
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hdmi@14530000 {
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compatible = "samsung,exynos4212-hdmi";
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reg = <0x14530000 0x70000>;
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interrupts = <0 95 0>;
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clocks = <&clock 413>, <&clock 143>, <&clock 768>,
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<&clock 158>, <&clock 640>;
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clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
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"sclk_hdmiphy", "mout_hdmi";
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status = "disabled";
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};
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mixer@14450000 {
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compatible = "samsung,exynos5420-mixer";
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reg = <0x14450000 0x10000>;
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interrupts = <0 94 0>;
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clocks = <&clock 431>, <&clock 143>;
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clock-names = "mixer", "sclk_hdmi";
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};
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gsc_0: video-scaler@13e00000 {
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compatible = "samsung,exynos5-gsc";
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reg = <0x13e00000 0x1000>;
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interrupts = <0 85 0>;
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clocks = <&clock 465>;
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clock-names = "gscl";
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samsung,power-domain = <&gsc_pd>;
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};
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gsc_1: video-scaler@13e10000 {
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compatible = "samsung,exynos5-gsc";
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reg = <0x13e10000 0x1000>;
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interrupts = <0 86 0>;
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clocks = <&clock 466>;
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clock-names = "gscl";
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samsung,power-domain = <&gsc_pd>;
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};
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};
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