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fb1c8f93d8
This patch (written by me and also containing many suggestions of Arjan van de Ven) does a major cleanup of the spinlock code. It does the following things: - consolidates and enhances the spinlock/rwlock debugging code - simplifies the asm/spinlock.h files - encapsulates the raw spinlock type and moves generic spinlock features (such as ->break_lock) into the generic code. - cleans up the spinlock code hierarchy to get rid of the spaghetti. Most notably there's now only a single variant of the debugging code, located in lib/spinlock_debug.c. (previously we had one SMP debugging variant per architecture, plus a separate generic one for UP builds) Also, i've enhanced the rwlock debugging facility, it will now track write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too. All locks have lockup detection now, which will work for both soft and hard spin/rwlock lockups. The arch-level include files now only contain the minimally necessary subset of the spinlock code - all the rest that can be generalized now lives in the generic headers: include/asm-i386/spinlock_types.h | 16 include/asm-x86_64/spinlock_types.h | 16 I have also split up the various spinlock variants into separate files, making it easier to see which does what. The new layout is: SMP | UP ----------------------------|----------------------------------- asm/spinlock_types_smp.h | linux/spinlock_types_up.h linux/spinlock_types.h | linux/spinlock_types.h asm/spinlock_smp.h | linux/spinlock_up.h linux/spinlock_api_smp.h | linux/spinlock_api_up.h linux/spinlock.h | linux/spinlock.h /* * here's the role of the various spinlock/rwlock related include files: * * on SMP builds: * * asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the * initializers * * linux/spinlock_types.h: * defines the generic type and initializers * * asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel * implementations, mostly inline assembly code * * (also included on UP-debug builds:) * * linux/spinlock_api_smp.h: * contains the prototypes for the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. * * on UP builds: * * linux/spinlock_type_up.h: * contains the generic, simplified UP spinlock type. * (which is an empty structure on non-debug builds) * * linux/spinlock_types.h: * defines the generic type and initializers * * linux/spinlock_up.h: * contains the __raw_spin_*()/etc. version of UP * builds. (which are NOPs on non-debug, non-preempt * builds) * * (included on UP-non-debug builds:) * * linux/spinlock_api_up.h: * builds the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. */ All SMP and UP architectures are converted by this patch. arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should be mostly fine. From: Grant Grundler <grundler@parisc-linux.org> Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU). Builds 32-bit SMP kernel (not booted or tested). I did not try to build non-SMP kernels. That should be trivial to fix up later if necessary. I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids some ugly nesting of linux/*.h and asm/*.h files. Those particular locks are well tested and contained entirely inside arch specific code. I do NOT expect any new issues to arise with them. If someone does ever need to use debug/metrics with them, then they will need to unravel this hairball between spinlocks, atomic ops, and bit ops that exist only because parisc has exactly one atomic instruction: LDCW (load and clear word). From: "Luck, Tony" <tony.luck@intel.com> ia64 fix Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjanv@infradead.org> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Cc: Matthew Wilcox <willy@debian.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se> Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
314 lines
7.4 KiB
C
314 lines
7.4 KiB
C
#ifndef _ASM_M32R_SPINLOCK_H
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#define _ASM_M32R_SPINLOCK_H
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/*
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* linux/include/asm-m32r/spinlock.h
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*
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* M32R version:
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* Copyright (C) 2001, 2002 Hitoshi Yamamoto
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* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
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*/
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#include <linux/config.h> /* CONFIG_DEBUG_SPINLOCK, CONFIG_SMP */
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#include <linux/compiler.h>
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#include <asm/atomic.h>
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#include <asm/page.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*
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* (the type definitions are in asm/spinlock_types.h)
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*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*/
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#define __raw_spin_is_locked(x) (*(volatile int *)(&(x)->slock) <= 0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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#define __raw_spin_unlock_wait(x) \
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do { cpu_relax(); } while (__raw_spin_is_locked(x))
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/**
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* __raw_spin_trylock - Try spin lock and return a result
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* @lock: Pointer to the lock variable
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*
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* __raw_spin_trylock() tries to get the lock and returns a result.
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* On the m32r, the result value is 1 (= Success) or 0 (= Failure).
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*/
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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int oldval;
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unsigned long tmp1, tmp2;
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/*
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* lock->slock : =1 : unlock
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* : <=0 : lock
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* {
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* oldval = lock->slock; <--+ need atomic operation
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* lock->slock = 0; <--+
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* }
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*/
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__asm__ __volatile__ (
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"# __raw_spin_trylock \n\t"
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"ldi %1, #0; \n\t"
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"mvfc %2, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%3")
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"lock %0, @%3; \n\t"
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"unlock %1, @%3; \n\t"
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"mvtc %2, psw; \n\t"
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: "=&r" (oldval), "=&r" (tmp1), "=&r" (tmp2)
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: "r" (&lock->slock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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return (oldval > 0);
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}
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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unsigned long tmp0, tmp1;
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/*
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* lock->slock : =1 : unlock
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* : <=0 : lock
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*
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* for ( ; ; ) {
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* lock->slock -= 1; <-- need atomic operation
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* if (lock->slock == 0) break;
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* for ( ; lock->slock <= 0 ; );
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* }
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*/
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__asm__ __volatile__ (
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"# __raw_spin_lock \n\t"
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".fillinsn \n"
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"1: \n\t"
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"mvfc %1, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%2")
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"lock %0, @%2; \n\t"
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"addi %0, #-1; \n\t"
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"unlock %0, @%2; \n\t"
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"mvtc %1, psw; \n\t"
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"bltz %0, 2f; \n\t"
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LOCK_SECTION_START(".balign 4 \n\t")
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".fillinsn \n"
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"2: \n\t"
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"ld %0, @%2; \n\t"
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"bgtz %0, 1b; \n\t"
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"bra 2b; \n\t"
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LOCK_SECTION_END
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: "=&r" (tmp0), "=&r" (tmp1)
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: "r" (&lock->slock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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mb();
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lock->slock = 1;
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}
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* On x86, we implement read-write locks as a 32-bit counter
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* with the high bit (sign) being the "contended" bit.
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*
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* The inline assembly is non-obvious. Think about it.
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*
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* Changed to use the same technique as rw semaphores. See
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* semaphore.h for details. -ben
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*/
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/**
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_read_can_lock(x) ((int)(x)->lock > 0)
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/**
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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unsigned long tmp0, tmp1;
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/*
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* rw->lock : >0 : unlock
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* : <=0 : lock
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*
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* for ( ; ; ) {
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* rw->lock -= 1; <-- need atomic operation
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* if (rw->lock >= 0) break;
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* rw->lock += 1; <-- need atomic operation
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* for ( ; rw->lock <= 0 ; );
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* }
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*/
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__asm__ __volatile__ (
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"# read_lock \n\t"
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".fillinsn \n"
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"1: \n\t"
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"mvfc %1, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%2")
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"lock %0, @%2; \n\t"
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"addi %0, #-1; \n\t"
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"unlock %0, @%2; \n\t"
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"mvtc %1, psw; \n\t"
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"bltz %0, 2f; \n\t"
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LOCK_SECTION_START(".balign 4 \n\t")
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".fillinsn \n"
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"2: \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%2")
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"lock %0, @%2; \n\t"
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"addi %0, #1; \n\t"
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"unlock %0, @%2; \n\t"
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"mvtc %1, psw; \n\t"
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".fillinsn \n"
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"3: \n\t"
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"ld %0, @%2; \n\t"
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"bgtz %0, 1b; \n\t"
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"bra 3b; \n\t"
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LOCK_SECTION_END
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: "=&r" (tmp0), "=&r" (tmp1)
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: "r" (&rw->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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unsigned long tmp0, tmp1, tmp2;
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/*
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* rw->lock : =RW_LOCK_BIAS_STR : unlock
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* : !=RW_LOCK_BIAS_STR : lock
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*
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* for ( ; ; ) {
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* rw->lock -= RW_LOCK_BIAS_STR; <-- need atomic operation
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* if (rw->lock == 0) break;
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* rw->lock += RW_LOCK_BIAS_STR; <-- need atomic operation
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* for ( ; rw->lock != RW_LOCK_BIAS_STR ; ) ;
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* }
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*/
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__asm__ __volatile__ (
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"# write_lock \n\t"
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"seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
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"or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
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".fillinsn \n"
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"1: \n\t"
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"mvfc %2, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r7", "%3")
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"lock %0, @%3; \n\t"
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"sub %0, %1; \n\t"
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"unlock %0, @%3; \n\t"
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"mvtc %2, psw; \n\t"
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"bnez %0, 2f; \n\t"
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LOCK_SECTION_START(".balign 4 \n\t")
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".fillinsn \n"
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"2: \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r7", "%3")
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"lock %0, @%3; \n\t"
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"add %0, %1; \n\t"
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"unlock %0, @%3; \n\t"
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"mvtc %2, psw; \n\t"
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".fillinsn \n"
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"3: \n\t"
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"ld %0, @%3; \n\t"
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"beq %0, %1, 1b; \n\t"
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"bra 3b; \n\t"
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LOCK_SECTION_END
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: "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r7"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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unsigned long tmp0, tmp1;
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__asm__ __volatile__ (
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"# read_unlock \n\t"
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"mvfc %1, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%2")
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"lock %0, @%2; \n\t"
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"addi %0, #1; \n\t"
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"unlock %0, @%2; \n\t"
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"mvtc %1, psw; \n\t"
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: "=&r" (tmp0), "=&r" (tmp1)
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: "r" (&rw->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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unsigned long tmp0, tmp1, tmp2;
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__asm__ __volatile__ (
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"# write_unlock \n\t"
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"seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
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"or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
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"mvfc %2, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r7", "%3")
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"lock %0, @%3; \n\t"
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"add %0, %1; \n\t"
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"unlock %0, @%3; \n\t"
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"mvtc %2, psw; \n\t"
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: "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r7"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
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static inline int __raw_write_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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return 1;
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atomic_add(RW_LOCK_BIAS, count);
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return 0;
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}
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#endif /* _ASM_M32R_SPINLOCK_H */
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