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f1f8b4948d
Currently the kernel expects the additional four IBAT and DBAT registers to be available, but doesn't enable these registers on 745x CPUs, which have them disabled after reset. Thus set the HIGH_BAT_EN bit in HID0 register, if the corresponding MMU feature is defined. Signed-off-by: Gerhard Pircher <gerhard_pircher@gmx.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
490 lines
11 KiB
ArmAsm
490 lines
11 KiB
ArmAsm
/*
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* This file contains low level CPU setup functions.
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* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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_GLOBAL(__setup_cpu_603)
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mflr r4
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BEGIN_MMU_FTR_SECTION
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li r10,0
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mtspr SPRN_SPRG4,r10 /* init SW LRU tracking */
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
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BEGIN_FTR_SECTION
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bl __init_fpu_registers
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END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
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bl setup_common_caches
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_604)
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mflr r4
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bl setup_common_caches
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bl setup_604_hid0
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_750)
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mflr r4
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bl __init_fpu_registers
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bl setup_common_caches
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bl setup_750_7400_hid0
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_750cx)
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mflr r4
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bl __init_fpu_registers
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bl setup_common_caches
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bl setup_750_7400_hid0
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bl setup_750cx
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_750fx)
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mflr r4
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bl __init_fpu_registers
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bl setup_common_caches
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bl setup_750_7400_hid0
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bl setup_750fx
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_7400)
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mflr r4
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bl __init_fpu_registers
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bl setup_7400_workarounds
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bl setup_common_caches
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bl setup_750_7400_hid0
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_7410)
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mflr r4
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bl __init_fpu_registers
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bl setup_7410_workarounds
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bl setup_common_caches
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bl setup_750_7400_hid0
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li r3,0
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mtspr SPRN_L2CR2,r3
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_745x)
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mflr r4
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bl setup_common_caches
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bl setup_745x_specifics
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mtlr r4
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blr
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/* Enable caches for 603's, 604, 750 & 7400 */
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setup_common_caches:
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mfspr r11,SPRN_HID0
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andi. r0,r11,HID0_DCE
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ori r11,r11,HID0_ICE|HID0_DCE
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ori r8,r11,HID0_ICFI
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bne 1f /* don't invalidate the D-cache */
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ori r8,r8,HID0_DCI /* unless it wasn't enabled */
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1: sync
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mtspr SPRN_HID0,r8 /* enable and invalidate caches */
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sync
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mtspr SPRN_HID0,r11 /* enable caches */
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sync
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isync
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blr
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/* 604, 604e, 604ev, ...
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* Enable superscalar execution & branch history table
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*/
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setup_604_hid0:
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mfspr r11,SPRN_HID0
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ori r11,r11,HID0_SIED|HID0_BHTE
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ori r8,r11,HID0_BTCD
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sync
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mtspr SPRN_HID0,r8 /* flush branch target address cache */
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sync /* on 604e/604r */
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mtspr SPRN_HID0,r11
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sync
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isync
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blr
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/* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
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* erratas we work around here.
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* Moto MPC710CE.pdf describes them, those are errata
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* #3, #4 and #5
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* Note that we assume the firmware didn't choose to
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* apply other workarounds (there are other ones documented
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* in the .pdf). It appear that Apple firmware only works
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* around #3 and with the same fix we use. We may want to
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* check if the CPU is using 60x bus mode in which case
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* the workaround for errata #4 is useless. Also, we may
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* want to explicitly clear HID0_NOPDST as this is not
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* needed once we have applied workaround #5 (though it's
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* not set by Apple's firmware at least).
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*/
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setup_7400_workarounds:
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mfpvr r3
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rlwinm r3,r3,0,20,31
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cmpwi 0,r3,0x0207
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ble 1f
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blr
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setup_7410_workarounds:
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mfpvr r3
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rlwinm r3,r3,0,20,31
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cmpwi 0,r3,0x0100
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bnelr
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1:
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mfspr r11,SPRN_MSSSR0
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/* Errata #3: Set L1OPQ_SIZE to 0x10 */
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rlwinm r11,r11,0,9,6
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oris r11,r11,0x0100
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/* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */
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oris r11,r11,0x0002
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/* Errata #5: Set DRLT_SIZE to 0x01 */
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rlwinm r11,r11,0,5,2
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oris r11,r11,0x0800
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sync
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mtspr SPRN_MSSSR0,r11
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sync
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isync
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blr
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/* 740/750/7400/7410
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* Enable Store Gathering (SGE), Address Brodcast (ABE),
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* Branch History Table (BHTE), Branch Target ICache (BTIC)
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* Dynamic Power Management (DPM), Speculative (SPD)
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* Clear Instruction cache throttling (ICTC)
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*/
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setup_750_7400_hid0:
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mfspr r11,SPRN_HID0
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ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
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oris r11,r11,HID0_DPM@h
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BEGIN_FTR_SECTION
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xori r11,r11,HID0_BTIC
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END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
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BEGIN_FTR_SECTION
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xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
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END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
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li r3,HID0_SPD
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andc r11,r11,r3 /* clear SPD: enable speculative */
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li r3,0
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mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
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isync
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mtspr SPRN_HID0,r11
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sync
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isync
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blr
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/* 750cx specific
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* Looks like we have to disable NAP feature for some PLL settings...
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* (waiting for confirmation)
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*/
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setup_750cx:
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mfspr r10, SPRN_HID1
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rlwinm r10,r10,4,28,31
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cmpwi cr0,r10,7
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cmpwi cr1,r10,9
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cmpwi cr2,r10,11
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
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bnelr
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lwz r6,CPU_SPEC_FEATURES(r5)
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li r7,CPU_FTR_CAN_NAP
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andc r6,r6,r7
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stw r6,CPU_SPEC_FEATURES(r5)
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blr
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/* 750fx specific
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*/
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setup_750fx:
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blr
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/* MPC 745x
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* Enable Store Gathering (SGE), Branch Folding (FOLD)
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* Branch History Table (BHTE), Branch Target ICache (BTIC)
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* Dynamic Power Management (DPM), Speculative (SPD)
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* Ensure our data cache instructions really operate.
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* Timebase has to be running or we wouldn't have made it here,
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* just ensure we don't disable it.
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* Clear Instruction cache throttling (ICTC)
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* Enable L2 HW prefetch
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*/
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setup_745x_specifics:
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/* We check for the presence of an L3 cache setup by
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* the firmware. If any, we disable NAP capability as
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* it's known to be bogus on rev 2.1 and earlier
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*/
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BEGIN_FTR_SECTION
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mfspr r11,SPRN_L3CR
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andis. r11,r11,L3CR_L3E@h
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beq 1f
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END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
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lwz r6,CPU_SPEC_FEATURES(r5)
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andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
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beq 1f
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li r7,CPU_FTR_CAN_NAP
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andc r6,r6,r7
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stw r6,CPU_SPEC_FEATURES(r5)
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1:
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mfspr r11,SPRN_HID0
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/* All of the bits we have to set.....
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*/
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ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
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ori r11,r11,HID0_LRSTK | HID0_BTIC
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oris r11,r11,HID0_DPM@h
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BEGIN_MMU_FTR_SECTION
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oris r11,r11,HID0_HIGH_BAT@h
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
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BEGIN_FTR_SECTION
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xori r11,r11,HID0_BTIC
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END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
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BEGIN_FTR_SECTION
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xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
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END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
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/* All of the bits we have to clear....
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*/
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li r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI
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andc r11,r11,r3 /* clear SPD: enable speculative */
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li r3,0
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mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
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isync
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mtspr SPRN_HID0,r11
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sync
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isync
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/* Enable L2 HW prefetch, if L2 is enabled
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*/
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mfspr r3,SPRN_L2CR
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andis. r3,r3,L2CR_L2E@h
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beqlr
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mfspr r3,SPRN_MSSCR0
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ori r3,r3,3
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sync
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mtspr SPRN_MSSCR0,r3
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sync
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isync
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blr
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/*
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* Initialize the FPU registers. This is needed to work around an errata
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* in some 750 cpus where using a not yet initialized FPU register after
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* power on reset may hang the CPU
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*/
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_GLOBAL(__init_fpu_registers)
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mfmsr r10
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ori r11,r10,MSR_FP
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mtmsr r11
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isync
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addis r9,r3,empty_zero_page@ha
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addi r9,r9,empty_zero_page@l
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REST_32FPRS(0,r9)
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sync
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mtmsr r10
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isync
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blr
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/* Definitions for the table use to save CPU states */
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#define CS_HID0 0
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#define CS_HID1 4
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#define CS_HID2 8
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#define CS_MSSCR0 12
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#define CS_MSSSR0 16
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#define CS_ICTRL 20
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#define CS_LDSTCR 24
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#define CS_LDSTDB 28
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#define CS_SIZE 32
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.data
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.balign L1_CACHE_BYTES
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cpu_state_storage:
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.space CS_SIZE
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.balign L1_CACHE_BYTES,0
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.text
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/* Called in normal context to backup CPU 0 state. This
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* does not include cache settings. This function is also
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* called for machine sleep. This does not include the MMU
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* setup, BATs, etc... but rather the "special" registers
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* like HID0, HID1, MSSCR0, etc...
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*/
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_GLOBAL(__save_cpu_setup)
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/* Some CR fields are volatile, we back it up all */
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mfcr r7
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/* Get storage ptr */
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lis r5,cpu_state_storage@h
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ori r5,r5,cpu_state_storage@l
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/* Save HID0 (common to all CONFIG_6xx cpus) */
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mfspr r3,SPRN_HID0
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stw r3,CS_HID0(r5)
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/* Now deal with CPU type dependent registers */
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mfspr r3,SPRN_PVR
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srwi r3,r3,16
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cmplwi cr0,r3,0x8000 /* 7450 */
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cmplwi cr1,r3,0x000c /* 7400 */
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cmplwi cr2,r3,0x800c /* 7410 */
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cmplwi cr3,r3,0x8001 /* 7455 */
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cmplwi cr4,r3,0x8002 /* 7457 */
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cmplwi cr5,r3,0x8003 /* 7447A */
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cmplwi cr6,r3,0x7000 /* 750FX */
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cmplwi cr7,r3,0x8004 /* 7448 */
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/* cr1 is 7400 || 7410 */
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cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
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/* cr0 is 74xx */
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cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
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bne 1f
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/* Backup 74xx specific regs */
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mfspr r4,SPRN_MSSCR0
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stw r4,CS_MSSCR0(r5)
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mfspr r4,SPRN_MSSSR0
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stw r4,CS_MSSSR0(r5)
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beq cr1,1f
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/* Backup 745x specific registers */
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mfspr r4,SPRN_HID1
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stw r4,CS_HID1(r5)
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mfspr r4,SPRN_ICTRL
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stw r4,CS_ICTRL(r5)
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mfspr r4,SPRN_LDSTCR
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stw r4,CS_LDSTCR(r5)
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mfspr r4,SPRN_LDSTDB
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stw r4,CS_LDSTDB(r5)
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1:
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bne cr6,1f
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/* Backup 750FX specific registers */
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mfspr r4,SPRN_HID1
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stw r4,CS_HID1(r5)
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/* If rev 2.x, backup HID2 */
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mfspr r3,SPRN_PVR
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andi. r3,r3,0xff00
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cmpwi cr0,r3,0x0200
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bne 1f
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mfspr r4,SPRN_HID2
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stw r4,CS_HID2(r5)
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1:
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mtcr r7
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blr
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/* Called with no MMU context (typically MSR:IR/DR off) to
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* restore CPU state as backed up by the previous
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* function. This does not include cache setting
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*/
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_GLOBAL(__restore_cpu_setup)
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/* Some CR fields are volatile, we back it up all */
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mfcr r7
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/* Get storage ptr */
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lis r5,(cpu_state_storage-KERNELBASE)@h
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ori r5,r5,cpu_state_storage@l
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/* Restore HID0 */
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lwz r3,CS_HID0(r5)
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sync
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isync
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mtspr SPRN_HID0,r3
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sync
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isync
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/* Now deal with CPU type dependent registers */
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mfspr r3,SPRN_PVR
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srwi r3,r3,16
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cmplwi cr0,r3,0x8000 /* 7450 */
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cmplwi cr1,r3,0x000c /* 7400 */
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cmplwi cr2,r3,0x800c /* 7410 */
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cmplwi cr3,r3,0x8001 /* 7455 */
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cmplwi cr4,r3,0x8002 /* 7457 */
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cmplwi cr5,r3,0x8003 /* 7447A */
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cmplwi cr6,r3,0x7000 /* 750FX */
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cmplwi cr7,r3,0x8004 /* 7448 */
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/* cr1 is 7400 || 7410 */
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cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
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/* cr0 is 74xx */
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cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
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bne 2f
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/* Restore 74xx specific regs */
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lwz r4,CS_MSSCR0(r5)
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sync
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mtspr SPRN_MSSCR0,r4
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sync
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isync
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lwz r4,CS_MSSSR0(r5)
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sync
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mtspr SPRN_MSSSR0,r4
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sync
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isync
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bne cr2,1f
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/* Clear 7410 L2CR2 */
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li r4,0
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mtspr SPRN_L2CR2,r4
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1: beq cr1,2f
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/* Restore 745x specific registers */
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lwz r4,CS_HID1(r5)
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sync
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mtspr SPRN_HID1,r4
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isync
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sync
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lwz r4,CS_ICTRL(r5)
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sync
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mtspr SPRN_ICTRL,r4
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isync
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sync
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lwz r4,CS_LDSTCR(r5)
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sync
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mtspr SPRN_LDSTCR,r4
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isync
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sync
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lwz r4,CS_LDSTDB(r5)
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sync
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mtspr SPRN_LDSTDB,r4
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isync
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sync
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2: bne cr6,1f
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/* Restore 750FX specific registers
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* that is restore HID2 on rev 2.x and PLL config & switch
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* to PLL 0 on all
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*/
|
|
/* If rev 2.x, restore HID2 with low voltage bit cleared */
|
|
mfspr r3,SPRN_PVR
|
|
andi. r3,r3,0xff00
|
|
cmpwi cr0,r3,0x0200
|
|
bne 4f
|
|
lwz r4,CS_HID2(r5)
|
|
rlwinm r4,r4,0,19,17
|
|
mtspr SPRN_HID2,r4
|
|
sync
|
|
4:
|
|
lwz r4,CS_HID1(r5)
|
|
rlwinm r5,r4,0,16,14
|
|
mtspr SPRN_HID1,r5
|
|
/* Wait for PLL to stabilize */
|
|
mftbl r5
|
|
3: mftbl r6
|
|
sub r6,r6,r5
|
|
cmplwi cr0,r6,10000
|
|
ble 3b
|
|
/* Setup final PLL */
|
|
mtspr SPRN_HID1,r4
|
|
1:
|
|
mtcr r7
|
|
blr
|
|
|