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linux-next/tools/testing/selftests/rseq/rseq.h
Linus Torvalds aa5b537b0e RISC-V Patches for the 5.18 Merge Window, Part 1
* Support for Sv57-based virtual memory.
 * Various improvements for the MicroChip PolarFire SOC and the
   associated Icicle dev board, which should allow upstream kernels to
   boot without any additional modifications.
 * An improved memmove() implementation.
 * Support for the new Ssconfpmf and SBI PMU extensions, which allows for
   a much more useful perf implementation on RISC-V systems.
 * Support for restartable sequences.
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Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:

 - Support for Sv57-based virtual memory.

 - Various improvements for the MicroChip PolarFire SOC and the
   associated Icicle dev board, which should allow upstream kernels to
   boot without any additional modifications.

 - An improved memmove() implementation.

 - Support for the new Ssconfpmf and SBI PMU extensions, which allows
   for a much more useful perf implementation on RISC-V systems.

 - Support for restartable sequences.

* tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits)
  rseq/selftests: Add support for RISC-V
  RISC-V: Add support for restartable sequence
  MAINTAINERS: Add entry for RISC-V PMU drivers
  Documentation: riscv: Remove the old documentation
  RISC-V: Add sscofpmf extension support
  RISC-V: Add perf platform driver based on SBI PMU extension
  RISC-V: Add RISC-V SBI PMU extension definitions
  RISC-V: Add a simple platform driver for RISC-V legacy perf
  RISC-V: Add a perf core library for pmu drivers
  RISC-V: Add CSR encodings for all HPMCOUNTERS
  RISC-V: Remove the current perf implementation
  RISC-V: Improve /proc/cpuinfo output for ISA extensions
  RISC-V: Do no continue isa string parsing without correct XLEN
  RISC-V: Implement multi-letter ISA extension probing framework
  RISC-V: Extract multi-letter extension names from "riscv, isa"
  RISC-V: Minimal parser for "riscv, isa" strings
  RISC-V: Correctly print supported extensions
  riscv: Fixed misaligned memory access. Fixed pointer comparison.
  MAINTAINERS: update riscv/microchip entry
  riscv: dts: microchip: add new peripherals to icicle kit device tree
  ...
2022-03-25 10:11:38 -07:00

178 lines
4.7 KiB
C

/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
/*
* rseq.h
*
* (C) Copyright 2016-2018 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
*/
#ifndef RSEQ_H
#define RSEQ_H
#include <stdint.h>
#include <stdbool.h>
#include <pthread.h>
#include <signal.h>
#include <sched.h>
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include "rseq-abi.h"
#include "compiler.h"
/*
* Empty code injection macros, override when testing.
* It is important to consider that the ASM injection macros need to be
* fully reentrant (e.g. do not modify the stack).
*/
#ifndef RSEQ_INJECT_ASM
#define RSEQ_INJECT_ASM(n)
#endif
#ifndef RSEQ_INJECT_C
#define RSEQ_INJECT_C(n)
#endif
#ifndef RSEQ_INJECT_INPUT
#define RSEQ_INJECT_INPUT
#endif
#ifndef RSEQ_INJECT_CLOBBER
#define RSEQ_INJECT_CLOBBER
#endif
#ifndef RSEQ_INJECT_FAILED
#define RSEQ_INJECT_FAILED
#endif
#include "rseq-thread-pointer.h"
/* Offset from the thread pointer to the rseq area. */
extern ptrdiff_t rseq_offset;
/* Size of the registered rseq area. 0 if the registration was
unsuccessful. */
extern unsigned int rseq_size;
/* Flags used during rseq registration. */
extern unsigned int rseq_flags;
static inline struct rseq_abi *rseq_get_abi(void)
{
return (struct rseq_abi *) ((uintptr_t) rseq_thread_pointer() + rseq_offset);
}
#define rseq_likely(x) __builtin_expect(!!(x), 1)
#define rseq_unlikely(x) __builtin_expect(!!(x), 0)
#define rseq_barrier() __asm__ __volatile__("" : : : "memory")
#define RSEQ_ACCESS_ONCE(x) (*(__volatile__ __typeof__(x) *)&(x))
#define RSEQ_WRITE_ONCE(x, v) __extension__ ({ RSEQ_ACCESS_ONCE(x) = (v); })
#define RSEQ_READ_ONCE(x) RSEQ_ACCESS_ONCE(x)
#define __rseq_str_1(x) #x
#define __rseq_str(x) __rseq_str_1(x)
#define rseq_log(fmt, args...) \
fprintf(stderr, fmt "(in %s() at " __FILE__ ":" __rseq_str(__LINE__)"\n", \
## args, __func__)
#define rseq_bug(fmt, args...) \
do { \
rseq_log(fmt, ##args); \
abort(); \
} while (0)
#if defined(__x86_64__) || defined(__i386__)
#include <rseq-x86.h>
#elif defined(__ARMEL__)
#include <rseq-arm.h>
#elif defined (__AARCH64EL__)
#include <rseq-arm64.h>
#elif defined(__PPC__)
#include <rseq-ppc.h>
#elif defined(__mips__)
#include <rseq-mips.h>
#elif defined(__s390__)
#include <rseq-s390.h>
#elif defined(__riscv)
#include <rseq-riscv.h>
#else
#error unsupported target
#endif
/*
* Register rseq for the current thread. This needs to be called once
* by any thread which uses restartable sequences, before they start
* using restartable sequences, to ensure restartable sequences
* succeed. A restartable sequence executed from a non-registered
* thread will always fail.
*/
int rseq_register_current_thread(void);
/*
* Unregister rseq for current thread.
*/
int rseq_unregister_current_thread(void);
/*
* Restartable sequence fallback for reading the current CPU number.
*/
int32_t rseq_fallback_current_cpu(void);
/*
* Values returned can be either the current CPU number, -1 (rseq is
* uninitialized), or -2 (rseq initialization has failed).
*/
static inline int32_t rseq_current_cpu_raw(void)
{
return RSEQ_ACCESS_ONCE(rseq_get_abi()->cpu_id);
}
/*
* Returns a possible CPU number, which is typically the current CPU.
* The returned CPU number can be used to prepare for an rseq critical
* section, which will confirm whether the cpu number is indeed the
* current one, and whether rseq is initialized.
*
* The CPU number returned by rseq_cpu_start should always be validated
* by passing it to a rseq asm sequence, or by comparing it to the
* return value of rseq_current_cpu_raw() if the rseq asm sequence
* does not need to be invoked.
*/
static inline uint32_t rseq_cpu_start(void)
{
return RSEQ_ACCESS_ONCE(rseq_get_abi()->cpu_id_start);
}
static inline uint32_t rseq_current_cpu(void)
{
int32_t cpu;
cpu = rseq_current_cpu_raw();
if (rseq_unlikely(cpu < 0))
cpu = rseq_fallback_current_cpu();
return cpu;
}
static inline void rseq_clear_rseq_cs(void)
{
RSEQ_WRITE_ONCE(rseq_get_abi()->rseq_cs.arch.ptr, 0);
}
/*
* rseq_prepare_unload() should be invoked by each thread executing a rseq
* critical section at least once between their last critical section and
* library unload of the library defining the rseq critical section (struct
* rseq_cs) or the code referred to by the struct rseq_cs start_ip and
* post_commit_offset fields. This also applies to use of rseq in code
* generated by JIT: rseq_prepare_unload() should be invoked at least once by
* each thread executing a rseq critical section before reclaim of the memory
* holding the struct rseq_cs or reclaim of the code pointed to by struct
* rseq_cs start_ip and post_commit_offset fields.
*/
static inline void rseq_prepare_unload(void)
{
rseq_clear_rseq_cs();
}
#endif /* RSEQ_H_ */