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aa5b537b0e
* Support for Sv57-based virtual memory. * Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. * An improved memmove() implementation. * Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. * Support for restartable sequences. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmI96FcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiQBFD/425+6xmoOru6Wiki3Ja0fqQToNrQyW IbmE/8AxUP7UxMvJSNzvQm8deXgklzvmegXCtnjwZZins971vMzzDSI83k/zn8I7 m5thVC9z01BjodV+pvIp/44hS6FesolOLzkVHksX0Zh6h0iidrc34Qf5HrqvvNfN CZ/4K1+E9ig5r9qZp4WdvocCXj+FzwF/30GjKoW9vwA599CEG/dCo+TNN9GKD6XS k+xiUGwlIRA+kCLSPFCi7ev9XPr1tCmQB7uB8Igcvr7Y3mWl8HKfajQVXBnXNRC3 ifbDxpx1elJiLPyf7Rza8jIDwDhLQdxBiwPgDgP9h9R4x0uF4efq8PzLzFlFmaE+ 9Z9thfykBb5dXYDFDje9bAOXvKnGk7Iqxdsz0qWo/ChEQawX1+11bJb0TNN8QTT9 YvlQfUXgb1dmEcj5yG2uVE1Y8L7YNLRMsZU3W3FbmPJZoavSOuU4x0yCGeLyv597 76af3nuBJ5v80Db97gu6St+HIACeevKflsZUf/8GS/p7d1DlvmrWzQUMEycxPTG9 UZpZak58jh7AqQ9JbLnavhwmeacY50vpZOw6QHGAHSN+8daCPlOHDG7Ver7Z+kNj +srJ7iKMvLnnaEjGNgavfxdqTOme1gv4LWs/JdHYMkpphqVN92xBDJnhXTPRVZiQ 0x39vK86qtB46A== =Omc6 -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for Sv57-based virtual memory. - Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. - An improved memmove() implementation. - Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. - Support for restartable sequences. * tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits) rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions riscv: Fixed misaligned memory access. Fixed pointer comparison. MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree ...
178 lines
4.7 KiB
C
178 lines
4.7 KiB
C
/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
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/*
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* rseq.h
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*
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* (C) Copyright 2016-2018 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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*/
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#ifndef RSEQ_H
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#define RSEQ_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <pthread.h>
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#include <signal.h>
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#include <sched.h>
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#include <errno.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stddef.h>
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#include "rseq-abi.h"
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#include "compiler.h"
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/*
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* Empty code injection macros, override when testing.
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* It is important to consider that the ASM injection macros need to be
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* fully reentrant (e.g. do not modify the stack).
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*/
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#ifndef RSEQ_INJECT_ASM
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#define RSEQ_INJECT_ASM(n)
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#endif
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#ifndef RSEQ_INJECT_C
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#define RSEQ_INJECT_C(n)
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#endif
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#ifndef RSEQ_INJECT_INPUT
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#define RSEQ_INJECT_INPUT
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#endif
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#ifndef RSEQ_INJECT_CLOBBER
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#define RSEQ_INJECT_CLOBBER
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#endif
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#ifndef RSEQ_INJECT_FAILED
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#define RSEQ_INJECT_FAILED
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#endif
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#include "rseq-thread-pointer.h"
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/* Offset from the thread pointer to the rseq area. */
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extern ptrdiff_t rseq_offset;
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/* Size of the registered rseq area. 0 if the registration was
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unsuccessful. */
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extern unsigned int rseq_size;
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/* Flags used during rseq registration. */
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extern unsigned int rseq_flags;
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static inline struct rseq_abi *rseq_get_abi(void)
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{
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return (struct rseq_abi *) ((uintptr_t) rseq_thread_pointer() + rseq_offset);
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}
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#define rseq_likely(x) __builtin_expect(!!(x), 1)
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#define rseq_unlikely(x) __builtin_expect(!!(x), 0)
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#define rseq_barrier() __asm__ __volatile__("" : : : "memory")
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#define RSEQ_ACCESS_ONCE(x) (*(__volatile__ __typeof__(x) *)&(x))
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#define RSEQ_WRITE_ONCE(x, v) __extension__ ({ RSEQ_ACCESS_ONCE(x) = (v); })
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#define RSEQ_READ_ONCE(x) RSEQ_ACCESS_ONCE(x)
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#define __rseq_str_1(x) #x
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#define __rseq_str(x) __rseq_str_1(x)
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#define rseq_log(fmt, args...) \
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fprintf(stderr, fmt "(in %s() at " __FILE__ ":" __rseq_str(__LINE__)"\n", \
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## args, __func__)
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#define rseq_bug(fmt, args...) \
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do { \
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rseq_log(fmt, ##args); \
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abort(); \
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} while (0)
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#if defined(__x86_64__) || defined(__i386__)
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#include <rseq-x86.h>
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#elif defined(__ARMEL__)
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#include <rseq-arm.h>
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#elif defined (__AARCH64EL__)
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#include <rseq-arm64.h>
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#elif defined(__PPC__)
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#include <rseq-ppc.h>
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#elif defined(__mips__)
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#include <rseq-mips.h>
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#elif defined(__s390__)
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#include <rseq-s390.h>
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#elif defined(__riscv)
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#include <rseq-riscv.h>
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#else
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#error unsupported target
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#endif
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/*
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* Register rseq for the current thread. This needs to be called once
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* by any thread which uses restartable sequences, before they start
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* using restartable sequences, to ensure restartable sequences
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* succeed. A restartable sequence executed from a non-registered
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* thread will always fail.
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*/
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int rseq_register_current_thread(void);
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/*
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* Unregister rseq for current thread.
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*/
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int rseq_unregister_current_thread(void);
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/*
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* Restartable sequence fallback for reading the current CPU number.
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*/
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int32_t rseq_fallback_current_cpu(void);
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/*
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* Values returned can be either the current CPU number, -1 (rseq is
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* uninitialized), or -2 (rseq initialization has failed).
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*/
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static inline int32_t rseq_current_cpu_raw(void)
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{
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return RSEQ_ACCESS_ONCE(rseq_get_abi()->cpu_id);
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}
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/*
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* Returns a possible CPU number, which is typically the current CPU.
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* The returned CPU number can be used to prepare for an rseq critical
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* section, which will confirm whether the cpu number is indeed the
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* current one, and whether rseq is initialized.
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*
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* The CPU number returned by rseq_cpu_start should always be validated
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* by passing it to a rseq asm sequence, or by comparing it to the
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* return value of rseq_current_cpu_raw() if the rseq asm sequence
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* does not need to be invoked.
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*/
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static inline uint32_t rseq_cpu_start(void)
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{
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return RSEQ_ACCESS_ONCE(rseq_get_abi()->cpu_id_start);
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}
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static inline uint32_t rseq_current_cpu(void)
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{
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int32_t cpu;
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cpu = rseq_current_cpu_raw();
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if (rseq_unlikely(cpu < 0))
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cpu = rseq_fallback_current_cpu();
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return cpu;
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}
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static inline void rseq_clear_rseq_cs(void)
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{
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RSEQ_WRITE_ONCE(rseq_get_abi()->rseq_cs.arch.ptr, 0);
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}
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/*
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* rseq_prepare_unload() should be invoked by each thread executing a rseq
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* critical section at least once between their last critical section and
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* library unload of the library defining the rseq critical section (struct
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* rseq_cs) or the code referred to by the struct rseq_cs start_ip and
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* post_commit_offset fields. This also applies to use of rseq in code
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* generated by JIT: rseq_prepare_unload() should be invoked at least once by
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* each thread executing a rseq critical section before reclaim of the memory
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* holding the struct rseq_cs or reclaim of the code pointed to by struct
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* rseq_cs start_ip and post_commit_offset fields.
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*/
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static inline void rseq_prepare_unload(void)
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{
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rseq_clear_rseq_cs();
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}
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#endif /* RSEQ_H_ */
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