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When PTEs are set to PROT_NONE the kernel just clears the Present bit and preserves the PFN, which creates attack surface for L1TF speculation speculation attacks. This is important inside guests, because L1TF speculation bypasses physical page remapping. While the host has its own migitations preventing leaking data from other VMs into the guest, this would still risk leaking the wrong page inside the current guest. This uses the same technique as Linus' swap entry patch: while an entry is is in PROTNONE state invert the complete PFN part part of it. This ensures that the the highest bit will point to non existing memory. The invert is done by pte/pmd_modify and pfn/pmd/pud_pte for PROTNONE and pte/pmd/pud_pfn undo it. This assume that no code path touches the PFN part of a PTE directly without using these primitives. This doesn't handle the case that MMIO is on the top of the CPU physical memory. If such an MMIO region was exposed by an unpriviledged driver for mmap it would be possible to attack some real memory. However this situation is all rather unlikely. For 32bit non PAE the inversion is not done because there are really not enough bits to protect anything. Q: Why does the guest need to be protected when the HyperVisor already has L1TF mitigations? A: Here's an example: Physical pages 1 2 get mapped into a guest as GPA 1 -> PA 2 GPA 2 -> PA 1 through EPT. The L1TF speculation ignores the EPT remapping. Now the guest kernel maps GPA 1 to process A and GPA 2 to process B, and they belong to different users and should be isolated. A sets the GPA 1 PA 2 PTE to PROT_NONE to bypass the EPT remapping and gets read access to the underlying physical page. Which in this case points to PA 2, so it can read process B's data, if it happened to be in L1, so isolation inside the guest is broken. There's nothing the hypervisor can do about this. This mitigation has to be done in the guest itself. [ tglx: Massaged changelog ] Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> Acked-by: Michal Hocko <mhocko@suse.com> Acked-by: Vlastimil Babka <vbabka@suse.cz> Acked-by: Dave Hansen <dave.hansen@intel.com>
33 lines
779 B
C
33 lines
779 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_PGTABLE_INVERT_H
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#define _ASM_PGTABLE_INVERT_H 1
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#ifndef __ASSEMBLY__
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static inline bool __pte_needs_invert(u64 val)
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{
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return (val & (_PAGE_PRESENT|_PAGE_PROTNONE)) == _PAGE_PROTNONE;
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}
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/* Get a mask to xor with the page table entry to get the correct pfn. */
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static inline u64 protnone_mask(u64 val)
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{
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return __pte_needs_invert(val) ? ~0ull : 0;
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}
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static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask)
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{
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/*
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* When a PTE transitions from NONE to !NONE or vice-versa
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* invert the PFN part to stop speculation.
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* pte_pfn undoes this when needed.
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*/
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if (__pte_needs_invert(oldval) != __pte_needs_invert(val))
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val = (val & ~mask) | (~val & mask);
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return val;
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}
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#endif /* __ASSEMBLY__ */
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#endif
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