mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-26 22:24:09 +08:00
62e59c4e69
Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
205 lines
4.0 KiB
C
205 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
|
* Copyright 2017~2018 NXP
|
|
*
|
|
* Author: Dong Aisheng <aisheng.dong@nxp.com>
|
|
*
|
|
*/
|
|
|
|
#include <linux/clk-provider.h>
|
|
#include <linux/err.h>
|
|
#include <linux/io.h>
|
|
#include <linux/iopoll.h>
|
|
#include <linux/slab.h>
|
|
|
|
#include "clk.h"
|
|
|
|
/**
|
|
* struct clk_pfdv2 - IMX PFD clock
|
|
* @clk_hw: clock source
|
|
* @reg: PFD register address
|
|
* @gate_bit: Gate bit offset
|
|
* @vld_bit: Valid bit offset
|
|
* @frac_off: PLL Fractional Divider offset
|
|
*/
|
|
|
|
struct clk_pfdv2 {
|
|
struct clk_hw hw;
|
|
void __iomem *reg;
|
|
u8 gate_bit;
|
|
u8 vld_bit;
|
|
u8 frac_off;
|
|
};
|
|
|
|
#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw)
|
|
|
|
#define CLK_PFDV2_FRAC_MASK 0x3f
|
|
|
|
#define LOCK_TIMEOUT_US USEC_PER_MSEC
|
|
|
|
static DEFINE_SPINLOCK(pfd_lock);
|
|
|
|
static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
|
|
{
|
|
u32 val;
|
|
|
|
return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit),
|
|
0, LOCK_TIMEOUT_US);
|
|
}
|
|
|
|
static int clk_pfdv2_enable(struct clk_hw *hw)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
spin_lock_irqsave(&pfd_lock, flags);
|
|
val = readl_relaxed(pfd->reg);
|
|
val &= ~(1 << pfd->gate_bit);
|
|
writel_relaxed(val, pfd->reg);
|
|
spin_unlock_irqrestore(&pfd_lock, flags);
|
|
|
|
return clk_pfdv2_wait(pfd);
|
|
}
|
|
|
|
static void clk_pfdv2_disable(struct clk_hw *hw)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
spin_lock_irqsave(&pfd_lock, flags);
|
|
val = readl_relaxed(pfd->reg);
|
|
val |= (1 << pfd->gate_bit);
|
|
writel_relaxed(val, pfd->reg);
|
|
spin_unlock_irqrestore(&pfd_lock, flags);
|
|
}
|
|
|
|
static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
u64 tmp = parent_rate;
|
|
u8 frac;
|
|
|
|
frac = (readl_relaxed(pfd->reg) >> pfd->frac_off)
|
|
& CLK_PFDV2_FRAC_MASK;
|
|
|
|
if (!frac) {
|
|
pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n",
|
|
clk_hw_get_name(hw));
|
|
return 0;
|
|
}
|
|
|
|
tmp *= 18;
|
|
do_div(tmp, frac);
|
|
|
|
return tmp;
|
|
}
|
|
|
|
static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *prate)
|
|
{
|
|
u64 tmp = *prate;
|
|
u8 frac;
|
|
|
|
tmp = tmp * 18 + rate / 2;
|
|
do_div(tmp, rate);
|
|
frac = tmp;
|
|
|
|
if (frac < 12)
|
|
frac = 12;
|
|
else if (frac > 35)
|
|
frac = 35;
|
|
|
|
tmp = *prate;
|
|
tmp *= 18;
|
|
do_div(tmp, frac);
|
|
|
|
return tmp;
|
|
}
|
|
|
|
static int clk_pfdv2_is_enabled(struct clk_hw *hw)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
|
|
if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
unsigned long flags;
|
|
u64 tmp = parent_rate;
|
|
u32 val;
|
|
u8 frac;
|
|
|
|
tmp = tmp * 18 + rate / 2;
|
|
do_div(tmp, rate);
|
|
frac = tmp;
|
|
if (frac < 12)
|
|
frac = 12;
|
|
else if (frac > 35)
|
|
frac = 35;
|
|
|
|
spin_lock_irqsave(&pfd_lock, flags);
|
|
val = readl_relaxed(pfd->reg);
|
|
val &= ~(CLK_PFDV2_FRAC_MASK << pfd->frac_off);
|
|
val |= frac << pfd->frac_off;
|
|
writel_relaxed(val, pfd->reg);
|
|
spin_unlock_irqrestore(&pfd_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct clk_ops clk_pfdv2_ops = {
|
|
.enable = clk_pfdv2_enable,
|
|
.disable = clk_pfdv2_disable,
|
|
.recalc_rate = clk_pfdv2_recalc_rate,
|
|
.round_rate = clk_pfdv2_round_rate,
|
|
.set_rate = clk_pfdv2_set_rate,
|
|
.is_enabled = clk_pfdv2_is_enabled,
|
|
};
|
|
|
|
struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
|
|
void __iomem *reg, u8 idx)
|
|
{
|
|
struct clk_init_data init;
|
|
struct clk_pfdv2 *pfd;
|
|
struct clk_hw *hw;
|
|
int ret;
|
|
|
|
WARN_ON(idx > 3);
|
|
|
|
pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
|
|
if (!pfd)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
pfd->reg = reg;
|
|
pfd->gate_bit = (idx + 1) * 8 - 1;
|
|
pfd->vld_bit = pfd->gate_bit - 1;
|
|
pfd->frac_off = idx * 8;
|
|
|
|
init.name = name;
|
|
init.ops = &clk_pfdv2_ops;
|
|
init.parent_names = &parent_name;
|
|
init.num_parents = 1;
|
|
init.flags = CLK_SET_RATE_GATE;
|
|
|
|
pfd->hw.init = &init;
|
|
|
|
hw = &pfd->hw;
|
|
ret = clk_hw_register(NULL, hw);
|
|
if (ret) {
|
|
kfree(pfd);
|
|
hw = ERR_PTR(ret);
|
|
}
|
|
|
|
return hw;
|
|
}
|