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6a918bade9
Flash device drivers initialize 'ecc_strength' in struct mtd_info, which is the maximum number of bit errors that can be corrected in one writesize region. Drivers using the nand interface intitialize 'strength' in struct nand_ecc_ctrl, which is the maximum number of bit errors that can be corrected in one ecc step. Nand infrastructure code translates this to 'ecc_strength'. Also for nand drivers, the nand infrastructure code sets ecc.strength for ecc modes NAND_ECC_SOFT, NAND_ECC_SOFT_BCH, and NAND_ECC_NONE. It is set in the driver for all other modes. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
839 lines
23 KiB
C
839 lines
23 KiB
C
/*
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* davinci_nand.c - NAND Flash Driver for DaVinci family chips
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*
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* Copyright © 2006 Texas Instruments.
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*
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* Port to 2.6.23 Copyright © 2008 by:
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* Sander Huijsen <Shuijsen@optelecom-nkf.com>
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* Troy Kisky <troy.kisky@boundarydevices.com>
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* Dirk Behme <Dirk.Behme@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/slab.h>
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#include <mach/nand.h>
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#include <mach/aemif.h>
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/*
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* This is a device driver for the NAND flash controller found on the
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* various DaVinci family chips. It handles up to four SoC chipselects,
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* and some flavors of secondary chipselect (e.g. based on A12) as used
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* with multichip packages.
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*
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* The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
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* available on chips like the DM355 and OMAP-L137 and needed with the
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* more error-prone MLC NAND chips.
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*
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* This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
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* outputs in a "wire-AND" configuration, with no per-chip signals.
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*/
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struct davinci_nand_info {
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struct mtd_info mtd;
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struct nand_chip chip;
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struct nand_ecclayout ecclayout;
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struct device *dev;
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struct clk *clk;
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bool is_readmode;
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void __iomem *base;
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void __iomem *vaddr;
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uint32_t ioaddr;
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uint32_t current_cs;
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uint32_t mask_chipsel;
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uint32_t mask_ale;
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uint32_t mask_cle;
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uint32_t core_chipsel;
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struct davinci_aemif_timing *timing;
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};
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static DEFINE_SPINLOCK(davinci_nand_lock);
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static bool ecc4_busy;
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#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
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static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
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int offset)
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{
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return __raw_readl(info->base + offset);
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}
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static inline void davinci_nand_writel(struct davinci_nand_info *info,
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int offset, unsigned long value)
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{
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__raw_writel(value, info->base + offset);
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}
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/*----------------------------------------------------------------------*/
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/*
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* Access to hardware control lines: ALE, CLE, secondary chipselect.
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*/
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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uint32_t addr = info->current_cs;
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struct nand_chip *nand = mtd->priv;
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/* Did the control lines change? */
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if (ctrl & NAND_CTRL_CHANGE) {
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if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
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addr |= info->mask_cle;
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else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
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addr |= info->mask_ale;
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nand->IO_ADDR_W = (void __iomem __force *)addr;
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}
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if (cmd != NAND_CMD_NONE)
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iowrite8(cmd, nand->IO_ADDR_W);
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}
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static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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uint32_t addr = info->ioaddr;
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/* maybe kick in a second chipselect */
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if (chip > 0)
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addr |= info->mask_chipsel;
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info->current_cs = addr;
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info->chip.IO_ADDR_W = (void __iomem __force *)addr;
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info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
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}
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/*----------------------------------------------------------------------*/
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/*
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* 1-bit hardware ECC ... context maintained for each core chipselect
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*/
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static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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return davinci_nand_readl(info, NANDF1ECC_OFFSET
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+ 4 * info->core_chipsel);
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}
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static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
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{
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struct davinci_nand_info *info;
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uint32_t nandcfr;
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unsigned long flags;
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info = to_davinci_nand(mtd);
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/* Reset ECC hardware */
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nand_davinci_readecc_1bit(mtd);
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spin_lock_irqsave(&davinci_nand_lock, flags);
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/* Restart ECC hardware */
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nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
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nandcfr |= BIT(8 + info->core_chipsel);
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davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
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spin_unlock_irqrestore(&davinci_nand_lock, flags);
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}
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/*
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* Read hardware ECC value and pack into three bytes
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*/
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static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
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unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
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/* invert so that erased block ecc is correct */
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ecc24 = ~ecc24;
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ecc_code[0] = (u_char)(ecc24);
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ecc_code[1] = (u_char)(ecc24 >> 8);
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ecc_code[2] = (u_char)(ecc24 >> 16);
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return 0;
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}
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static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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struct nand_chip *chip = mtd->priv;
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uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
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(read_ecc[2] << 16);
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uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
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(calc_ecc[2] << 16);
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uint32_t diff = eccCalc ^ eccNand;
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if (diff) {
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if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
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/* Correctable error */
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if ((diff >> (12 + 3)) < chip->ecc.size) {
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dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
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return 1;
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} else {
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return -1;
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}
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} else if (!(diff & (diff - 1))) {
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/* Single bit ECC error in the ECC itself,
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* nothing to fix */
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return 1;
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} else {
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/* Uncorrectable error */
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return -1;
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}
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}
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return 0;
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}
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/*----------------------------------------------------------------------*/
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/*
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* 4-bit hardware ECC ... context maintained over entire AEMIF
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*
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* This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
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* since that forces use of a problematic "infix OOB" layout.
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* Among other things, it trashes manufacturer bad block markers.
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* Also, and specific to this hardware, it ECC-protects the "prepad"
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* in the OOB ... while having ECC protection for parts of OOB would
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* seem useful, the current MTD stack sometimes wants to update the
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* OOB without recomputing ECC.
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*/
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static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&davinci_nand_lock, flags);
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/* Start 4-bit ECC calculation for read/write */
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val = davinci_nand_readl(info, NANDFCR_OFFSET);
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val &= ~(0x03 << 4);
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val |= (info->core_chipsel << 4) | BIT(12);
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davinci_nand_writel(info, NANDFCR_OFFSET, val);
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info->is_readmode = (mode == NAND_ECC_READ);
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spin_unlock_irqrestore(&davinci_nand_lock, flags);
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}
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/* Read raw ECC code after writing to NAND. */
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static void
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nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
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{
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const u32 mask = 0x03ff03ff;
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code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
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code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
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code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
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code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
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}
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/* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
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static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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u32 raw_ecc[4], *p;
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unsigned i;
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/* After a read, terminate ECC calculation by a dummy read
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* of some 4-bit ECC register. ECC covers everything that
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* was read; correct() just uses the hardware state, so
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* ecc_code is not needed.
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*/
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if (info->is_readmode) {
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davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
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return 0;
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}
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/* Pack eight raw 10-bit ecc values into ten bytes, making
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* two passes which each convert four values (in upper and
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* lower halves of two 32-bit words) into five bytes. The
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* ROM boot loader uses this same packing scheme.
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*/
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nand_davinci_readecc_4bit(info, raw_ecc);
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for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
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*ecc_code++ = p[0] & 0xff;
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*ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
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*ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
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*ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
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*ecc_code++ = (p[1] >> 18) & 0xff;
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}
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return 0;
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}
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/* Correct up to 4 bits in data we just read, using state left in the
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* hardware plus the ecc_code computed when it was first written.
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*/
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static int nand_davinci_correct_4bit(struct mtd_info *mtd,
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u_char *data, u_char *ecc_code, u_char *null)
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{
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int i;
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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unsigned short ecc10[8];
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unsigned short *ecc16;
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u32 syndrome[4];
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u32 ecc_state;
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unsigned num_errors, corrected;
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unsigned long timeo;
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/* All bytes 0xff? It's an erased page; ignore its ECC. */
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for (i = 0; i < 10; i++) {
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if (ecc_code[i] != 0xff)
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goto compare;
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}
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return 0;
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compare:
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/* Unpack ten bytes into eight 10 bit values. We know we're
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* little-endian, and use type punning for less shifting/masking.
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*/
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if (WARN_ON(0x01 & (unsigned) ecc_code))
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return -EINVAL;
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ecc16 = (unsigned short *)ecc_code;
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ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
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ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
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ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
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ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
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ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
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ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
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ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
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ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
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/* Tell ECC controller about the expected ECC codes. */
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for (i = 7; i >= 0; i--)
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davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
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/* Allow time for syndrome calculation ... then read it.
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* A syndrome of all zeroes 0 means no detected errors.
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*/
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davinci_nand_readl(info, NANDFSR_OFFSET);
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nand_davinci_readecc_4bit(info, syndrome);
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if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
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return 0;
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/*
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* Clear any previous address calculation by doing a dummy read of an
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* error address register.
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*/
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davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
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/* Start address calculation, and wait for it to complete.
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* We _could_ start reading more data while this is working,
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* to speed up the overall page read.
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*/
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davinci_nand_writel(info, NANDFCR_OFFSET,
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davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
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/*
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* ECC_STATE field reads 0x3 (Error correction complete) immediately
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* after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
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* begin trying to poll for the state, you may fall right out of your
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* loop without any of the correction calculations having taken place.
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* The recommendation from the hardware team is to initially delay as
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* long as ECC_STATE reads less than 4. After that, ECC HW has entered
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* correction state.
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*/
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timeo = jiffies + usecs_to_jiffies(100);
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do {
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ecc_state = (davinci_nand_readl(info,
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NANDFSR_OFFSET) >> 8) & 0x0f;
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cpu_relax();
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} while ((ecc_state < 4) && time_before(jiffies, timeo));
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for (;;) {
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u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
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switch ((fsr >> 8) & 0x0f) {
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case 0: /* no error, should not happen */
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davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
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return 0;
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case 1: /* five or more errors detected */
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davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
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return -EIO;
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case 2: /* error addresses computed */
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case 3:
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num_errors = 1 + ((fsr >> 16) & 0x03);
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goto correct;
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default: /* still working on it */
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cpu_relax();
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continue;
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}
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}
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correct:
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/* correct each error */
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for (i = 0, corrected = 0; i < num_errors; i++) {
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int error_address, error_value;
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if (i > 1) {
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error_address = davinci_nand_readl(info,
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NAND_ERR_ADD2_OFFSET);
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error_value = davinci_nand_readl(info,
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NAND_ERR_ERRVAL2_OFFSET);
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} else {
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error_address = davinci_nand_readl(info,
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NAND_ERR_ADD1_OFFSET);
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error_value = davinci_nand_readl(info,
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NAND_ERR_ERRVAL1_OFFSET);
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}
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if (i & 1) {
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error_address >>= 16;
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error_value >>= 16;
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}
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error_address &= 0x3ff;
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error_address = (512 + 7) - error_address;
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if (error_address < 512) {
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data[error_address] ^= error_value;
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corrected++;
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}
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}
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return corrected;
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}
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/*----------------------------------------------------------------------*/
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/*
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* NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
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* how these chips are normally wired. This translates to both 8 and 16
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* bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
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*
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* For now we assume that configuration, or any other one which ignores
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* the two LSBs for NAND access ... so we can issue 32-bit reads/writes
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* and have that transparently morphed into multiple NAND operations.
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*/
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static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
|
|
ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
|
|
else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
|
|
ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
|
|
else
|
|
ioread8_rep(chip->IO_ADDR_R, buf, len);
|
|
}
|
|
|
|
static void nand_davinci_write_buf(struct mtd_info *mtd,
|
|
const uint8_t *buf, int len)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
|
|
iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
|
|
else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
|
|
iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
|
|
else
|
|
iowrite8_rep(chip->IO_ADDR_R, buf, len);
|
|
}
|
|
|
|
/*
|
|
* Check hardware register for wait status. Returns 1 if device is ready,
|
|
* 0 if it is still busy.
|
|
*/
|
|
static int nand_davinci_dev_ready(struct mtd_info *mtd)
|
|
{
|
|
struct davinci_nand_info *info = to_davinci_nand(mtd);
|
|
|
|
return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
|
|
}
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
/* An ECC layout for using 4-bit ECC with small-page flash, storing
|
|
* ten ECC bytes plus the manufacturer's bad block marker byte, and
|
|
* and not overlapping the default BBT markers.
|
|
*/
|
|
static struct nand_ecclayout hwecc4_small __initconst = {
|
|
.eccbytes = 10,
|
|
.eccpos = { 0, 1, 2, 3, 4,
|
|
/* offset 5 holds the badblock marker */
|
|
6, 7,
|
|
13, 14, 15, },
|
|
.oobfree = {
|
|
{.offset = 8, .length = 5, },
|
|
{.offset = 16, },
|
|
},
|
|
};
|
|
|
|
/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
|
|
* storing ten ECC bytes plus the manufacturer's bad block marker byte,
|
|
* and not overlapping the default BBT markers.
|
|
*/
|
|
static struct nand_ecclayout hwecc4_2048 __initconst = {
|
|
.eccbytes = 40,
|
|
.eccpos = {
|
|
/* at the end of spare sector */
|
|
24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
|
|
34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
|
|
44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
|
|
54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
|
|
},
|
|
.oobfree = {
|
|
/* 2 bytes at offset 0 hold manufacturer badblock markers */
|
|
{.offset = 2, .length = 22, },
|
|
/* 5 bytes at offset 8 hold BBT markers */
|
|
/* 8 bytes at offset 16 hold JFFS2 clean markers */
|
|
},
|
|
};
|
|
|
|
static int __init nand_davinci_probe(struct platform_device *pdev)
|
|
{
|
|
struct davinci_nand_pdata *pdata = pdev->dev.platform_data;
|
|
struct davinci_nand_info *info;
|
|
struct resource *res1;
|
|
struct resource *res2;
|
|
void __iomem *vaddr;
|
|
void __iomem *base;
|
|
int ret;
|
|
uint32_t val;
|
|
nand_ecc_modes_t ecc_mode;
|
|
|
|
/* insist on board-specific configuration */
|
|
if (!pdata)
|
|
return -ENODEV;
|
|
|
|
/* which external chipselect will we be managing? */
|
|
if (pdev->id < 0 || pdev->id > 3)
|
|
return -ENODEV;
|
|
|
|
info = kzalloc(sizeof(*info), GFP_KERNEL);
|
|
if (!info) {
|
|
dev_err(&pdev->dev, "unable to allocate memory\n");
|
|
ret = -ENOMEM;
|
|
goto err_nomem;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, info);
|
|
|
|
res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
if (!res1 || !res2) {
|
|
dev_err(&pdev->dev, "resource missing\n");
|
|
ret = -EINVAL;
|
|
goto err_nomem;
|
|
}
|
|
|
|
vaddr = ioremap(res1->start, resource_size(res1));
|
|
base = ioremap(res2->start, resource_size(res2));
|
|
if (!vaddr || !base) {
|
|
dev_err(&pdev->dev, "ioremap failed\n");
|
|
ret = -EINVAL;
|
|
goto err_ioremap;
|
|
}
|
|
|
|
info->dev = &pdev->dev;
|
|
info->base = base;
|
|
info->vaddr = vaddr;
|
|
|
|
info->mtd.priv = &info->chip;
|
|
info->mtd.name = dev_name(&pdev->dev);
|
|
info->mtd.owner = THIS_MODULE;
|
|
|
|
info->mtd.dev.parent = &pdev->dev;
|
|
|
|
info->chip.IO_ADDR_R = vaddr;
|
|
info->chip.IO_ADDR_W = vaddr;
|
|
info->chip.chip_delay = 0;
|
|
info->chip.select_chip = nand_davinci_select_chip;
|
|
|
|
/* options such as NAND_BBT_USE_FLASH */
|
|
info->chip.bbt_options = pdata->bbt_options;
|
|
/* options such as 16-bit widths */
|
|
info->chip.options = pdata->options;
|
|
info->chip.bbt_td = pdata->bbt_td;
|
|
info->chip.bbt_md = pdata->bbt_md;
|
|
info->timing = pdata->timing;
|
|
|
|
info->ioaddr = (uint32_t __force) vaddr;
|
|
|
|
info->current_cs = info->ioaddr;
|
|
info->core_chipsel = pdev->id;
|
|
info->mask_chipsel = pdata->mask_chipsel;
|
|
|
|
/* use nandboot-capable ALE/CLE masks by default */
|
|
info->mask_ale = pdata->mask_ale ? : MASK_ALE;
|
|
info->mask_cle = pdata->mask_cle ? : MASK_CLE;
|
|
|
|
/* Set address of hardware control function */
|
|
info->chip.cmd_ctrl = nand_davinci_hwcontrol;
|
|
info->chip.dev_ready = nand_davinci_dev_ready;
|
|
|
|
/* Speed up buffer I/O */
|
|
info->chip.read_buf = nand_davinci_read_buf;
|
|
info->chip.write_buf = nand_davinci_write_buf;
|
|
|
|
/* Use board-specific ECC config */
|
|
ecc_mode = pdata->ecc_mode;
|
|
|
|
ret = -EINVAL;
|
|
switch (ecc_mode) {
|
|
case NAND_ECC_NONE:
|
|
case NAND_ECC_SOFT:
|
|
pdata->ecc_bits = 0;
|
|
break;
|
|
case NAND_ECC_HW:
|
|
if (pdata->ecc_bits == 4) {
|
|
/* No sanity checks: CPUs must support this,
|
|
* and the chips may not use NAND_BUSWIDTH_16.
|
|
*/
|
|
|
|
/* No sharing 4-bit hardware between chipselects yet */
|
|
spin_lock_irq(&davinci_nand_lock);
|
|
if (ecc4_busy)
|
|
ret = -EBUSY;
|
|
else
|
|
ecc4_busy = true;
|
|
spin_unlock_irq(&davinci_nand_lock);
|
|
|
|
if (ret == -EBUSY)
|
|
goto err_ecc;
|
|
|
|
info->chip.ecc.calculate = nand_davinci_calculate_4bit;
|
|
info->chip.ecc.correct = nand_davinci_correct_4bit;
|
|
info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
|
|
info->chip.ecc.bytes = 10;
|
|
} else {
|
|
info->chip.ecc.calculate = nand_davinci_calculate_1bit;
|
|
info->chip.ecc.correct = nand_davinci_correct_1bit;
|
|
info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
|
|
info->chip.ecc.bytes = 3;
|
|
}
|
|
info->chip.ecc.size = 512;
|
|
info->chip.ecc.strength = pdata->ecc_bits;
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
goto err_ecc;
|
|
}
|
|
info->chip.ecc.mode = ecc_mode;
|
|
|
|
info->clk = clk_get(&pdev->dev, "aemif");
|
|
if (IS_ERR(info->clk)) {
|
|
ret = PTR_ERR(info->clk);
|
|
dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
|
|
goto err_clk;
|
|
}
|
|
|
|
ret = clk_enable(info->clk);
|
|
if (ret < 0) {
|
|
dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
|
|
ret);
|
|
goto err_clk_enable;
|
|
}
|
|
|
|
/*
|
|
* Setup Async configuration register in case we did not boot from
|
|
* NAND and so bootloader did not bother to set it up.
|
|
*/
|
|
val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4);
|
|
|
|
/* Extended Wait is not valid and Select Strobe mode is not used */
|
|
val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
|
|
if (info->chip.options & NAND_BUSWIDTH_16)
|
|
val |= 0x1;
|
|
|
|
davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val);
|
|
|
|
ret = 0;
|
|
if (info->timing)
|
|
ret = davinci_aemif_setup_timing(info->timing, info->base,
|
|
info->core_chipsel);
|
|
if (ret < 0) {
|
|
dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
|
|
goto err_timing;
|
|
}
|
|
|
|
spin_lock_irq(&davinci_nand_lock);
|
|
|
|
/* put CSxNAND into NAND mode */
|
|
val = davinci_nand_readl(info, NANDFCR_OFFSET);
|
|
val |= BIT(info->core_chipsel);
|
|
davinci_nand_writel(info, NANDFCR_OFFSET, val);
|
|
|
|
spin_unlock_irq(&davinci_nand_lock);
|
|
|
|
/* Scan to find existence of the device(s) */
|
|
ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
|
|
if (ret < 0) {
|
|
dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
|
|
goto err_scan;
|
|
}
|
|
|
|
/* Update ECC layout if needed ... for 1-bit HW ECC, the default
|
|
* is OK, but it allocates 6 bytes when only 3 are needed (for
|
|
* each 512 bytes). For the 4-bit HW ECC, that default is not
|
|
* usable: 10 bytes are needed, not 6.
|
|
*/
|
|
if (pdata->ecc_bits == 4) {
|
|
int chunks = info->mtd.writesize / 512;
|
|
|
|
if (!chunks || info->mtd.oobsize < 16) {
|
|
dev_dbg(&pdev->dev, "too small\n");
|
|
ret = -EINVAL;
|
|
goto err_scan;
|
|
}
|
|
|
|
/* For small page chips, preserve the manufacturer's
|
|
* badblock marking data ... and make sure a flash BBT
|
|
* table marker fits in the free bytes.
|
|
*/
|
|
if (chunks == 1) {
|
|
info->ecclayout = hwecc4_small;
|
|
info->ecclayout.oobfree[1].length =
|
|
info->mtd.oobsize - 16;
|
|
goto syndrome_done;
|
|
}
|
|
if (chunks == 4) {
|
|
info->ecclayout = hwecc4_2048;
|
|
info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
|
|
goto syndrome_done;
|
|
}
|
|
|
|
/* 4KiB page chips are not yet supported. The eccpos from
|
|
* nand_ecclayout cannot hold 80 bytes and change to eccpos[]
|
|
* breaks userspace ioctl interface with mtd-utils. Once we
|
|
* resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
|
|
* for the 4KiB page chips.
|
|
*
|
|
* TODO: Note that nand_ecclayout has now been expanded and can
|
|
* hold plenty of OOB entries.
|
|
*/
|
|
dev_warn(&pdev->dev, "no 4-bit ECC support yet "
|
|
"for 4KiB-page NAND\n");
|
|
ret = -EIO;
|
|
goto err_scan;
|
|
|
|
syndrome_done:
|
|
info->chip.ecc.layout = &info->ecclayout;
|
|
}
|
|
|
|
ret = nand_scan_tail(&info->mtd);
|
|
if (ret < 0)
|
|
goto err_scan;
|
|
|
|
ret = mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
|
|
pdata->nr_parts);
|
|
|
|
if (ret < 0)
|
|
goto err_scan;
|
|
|
|
val = davinci_nand_readl(info, NRCSR_OFFSET);
|
|
dev_info(&pdev->dev, "controller rev. %d.%d\n",
|
|
(val >> 8) & 0xff, val & 0xff);
|
|
|
|
return 0;
|
|
|
|
err_scan:
|
|
err_timing:
|
|
clk_disable(info->clk);
|
|
|
|
err_clk_enable:
|
|
clk_put(info->clk);
|
|
|
|
spin_lock_irq(&davinci_nand_lock);
|
|
if (ecc_mode == NAND_ECC_HW_SYNDROME)
|
|
ecc4_busy = false;
|
|
spin_unlock_irq(&davinci_nand_lock);
|
|
|
|
err_ecc:
|
|
err_clk:
|
|
err_ioremap:
|
|
if (base)
|
|
iounmap(base);
|
|
if (vaddr)
|
|
iounmap(vaddr);
|
|
|
|
err_nomem:
|
|
kfree(info);
|
|
return ret;
|
|
}
|
|
|
|
static int __exit nand_davinci_remove(struct platform_device *pdev)
|
|
{
|
|
struct davinci_nand_info *info = platform_get_drvdata(pdev);
|
|
|
|
spin_lock_irq(&davinci_nand_lock);
|
|
if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
|
|
ecc4_busy = false;
|
|
spin_unlock_irq(&davinci_nand_lock);
|
|
|
|
iounmap(info->base);
|
|
iounmap(info->vaddr);
|
|
|
|
nand_release(&info->mtd);
|
|
|
|
clk_disable(info->clk);
|
|
clk_put(info->clk);
|
|
|
|
kfree(info);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver nand_davinci_driver = {
|
|
.remove = __exit_p(nand_davinci_remove),
|
|
.driver = {
|
|
.name = "davinci_nand",
|
|
},
|
|
};
|
|
MODULE_ALIAS("platform:davinci_nand");
|
|
|
|
static int __init nand_davinci_init(void)
|
|
{
|
|
return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
|
|
}
|
|
module_init(nand_davinci_init);
|
|
|
|
static void __exit nand_davinci_exit(void)
|
|
{
|
|
platform_driver_unregister(&nand_davinci_driver);
|
|
}
|
|
module_exit(nand_davinci_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Texas Instruments");
|
|
MODULE_DESCRIPTION("Davinci NAND flash driver");
|
|
|