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On some socs Mali Utgard gpus have both soc power-domains and external supplying regulators, so add an optional power-domains property for reference. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org>
111 lines
3.2 KiB
Plaintext
111 lines
3.2 KiB
Plaintext
ARM Mali Utgard GPU
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===================
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Required properties:
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- compatible
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* Must be one of the following:
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+ "arm,mali-300"
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+ "arm,mali-400"
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+ "arm,mali-450"
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* And, optionally, one of the vendor specific compatible:
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+ allwinner,sun4i-a10-mali
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+ allwinner,sun7i-a20-mali
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+ allwinner,sun50i-h5-mali
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+ amlogic,meson-gxbb-mali
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+ amlogic,meson-gxl-mali
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+ rockchip,rk3036-mali
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+ rockchip,rk3066-mali
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+ rockchip,rk3188-mali
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+ rockchip,rk3228-mali
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+ stericsson,db8500-mali
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- reg: Physical base address and length of the GPU registers
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- interrupts: an entry for each entry in interrupt-names.
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See ../interrupt-controller/interrupts.txt for details.
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- interrupt-names:
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* ppX: Pixel Processor X interrupt (X from 0 to 7)
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* ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
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* pp: Pixel Processor broadcast interrupt (mali-450 only)
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* gp: Geometry Processor interrupt
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* gpmmu: Geometry Processor MMU interrupt
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- clocks: an entry for each entry in clock-names
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- clock-names:
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* bus: bus clock for the GPU
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* core: clock driving the GPU itself
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Optional properties:
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- interrupt-names and interrupts:
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* pmu: Power Management Unit interrupt, if implemented in hardware
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- memory-region:
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Memory region to allocate from, as defined in
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Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
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- mali-supply:
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Phandle to regulator for the Mali device, as defined in
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Documentation/devicetree/bindings/regulator/regulator.txt for details.
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- operating-points-v2:
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Operating Points for the GPU, as defined in
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Documentation/devicetree/bindings/opp/opp.txt
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- power-domains:
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A power domain consumer specifier as defined in
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Documentation/devicetree/bindings/power/power_domain.txt
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Vendor-specific bindings
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------------------------
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The Mali GPU is integrated very differently from one SoC to
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another. In order to accomodate those differences, you have the option
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to specify one more vendor-specific compatible, among:
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- allwinner,sun4i-a10-mali
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Required properties:
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* resets: phandle to the reset line for the GPU
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- allwinner,sun7i-a20-mali
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Required properties:
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* resets: phandle to the reset line for the GPU
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- allwinner,sun50i-h5-mali
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Required properties:
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* resets: phandle to the reset line for the GPU
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- Rockchip variants:
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Required properties:
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* resets: phandle to the reset line for the GPU
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- stericsson,db8500-mali
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Required properties:
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* interrupt-names and interrupts:
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+ combined: combined interrupt of all of the above lines
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Example:
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mali: gpu@1c40000 {
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compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
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reg = <0x01c40000 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp0",
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"ppmmu0",
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"pp1",
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"ppmmu1",
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"pmu";
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clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
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clock-names = "bus", "core";
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resets = <&ccu RST_BUS_GPU>;
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};
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