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26ec99b105
The mwave driver has its own macros for the BOOLEAN type and the
TRUE/FALSE values. This is redundant because the kernel already
has bool/true/false, and it clashes with the ACPI headers that
also define these types. The linux/acpi.h header is now included
implicitly from mwave through the mc146818rtc.h header, as
reported by Stephen Rothwell:
In file included from drivers/char/mwave/smapi.c:51:0:
drivers/char/mwave/smapi.h:52:0: warning: "TRUE" redefined
#define TRUE 1
^
In file included from include/acpi/acpi.h:58:0,
from include/linux/acpi.h:33,
from include/linux/mc146818rtc.h:21,
from drivers/char/mwave/smapi.c:50:
include/acpi/actypes.h:438:0: note: this is the location of the previous definition
#define TRUE (1 == 1)
^
This removes the private types from mwave and uses the standard
types instead.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Fixes: fd09cc80165c ("rtc: cmos: move mc146818rtc code out of asm-generic/rtc.h")
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
359 lines
14 KiB
C
359 lines
14 KiB
C
/*
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*
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* 3780i.h -- declarations for 3780i.c
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*
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*
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* Written By: Mike Sullivan IBM Corporation
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*
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* Copyright (C) 1999 IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* NO WARRANTY
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* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
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* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
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* solely responsible for determining the appropriateness of using and
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* distributing the Program and assumes all risks associated with its
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* exercise of rights under this Agreement, including but not limited to
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* the risks and costs of program errors, damage to or loss of data,
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* programs or equipment, and unavailability or interruption of operations.
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*
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* DISCLAIMER OF LIABILITY
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* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
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* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*
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* 10/23/2000 - Alpha Release
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* First release to the public
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*/
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#ifndef _LINUX_3780I_H
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#define _LINUX_3780I_H
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#include <asm/io.h>
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/* DSP I/O port offsets and definitions */
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#define DSP_IsaSlaveControl 0x0000 /* ISA slave control register */
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#define DSP_IsaSlaveStatus 0x0001 /* ISA slave status register */
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#define DSP_ConfigAddress 0x0002 /* General config address register */
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#define DSP_ConfigData 0x0003 /* General config data register */
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#define DSP_HBridgeControl 0x0002 /* HBridge control register */
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#define DSP_MsaAddrLow 0x0004 /* MSP System Address, low word */
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#define DSP_MsaAddrHigh 0x0006 /* MSP System Address, high word */
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#define DSP_MsaDataDSISHigh 0x0008 /* MSA data register: d-store word or high byte of i-store */
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#define DSP_MsaDataISLow 0x000A /* MSA data register: low word of i-store */
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#define DSP_ReadAndClear 0x000C /* MSA read and clear data register */
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#define DSP_Interrupt 0x000E /* Interrupt register (IPC source) */
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typedef struct {
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unsigned char ClockControl:1; /* RW: Clock control: 0=normal, 1=stop 3780i clocks */
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unsigned char SoftReset:1; /* RW: Soft reset 0=normal, 1=soft reset active */
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unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
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unsigned char Reserved:5; /* 0: Reserved */
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} DSP_ISA_SLAVE_CONTROL;
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typedef struct {
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unsigned short EnableDspInt:1; /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
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unsigned short MemAutoInc:1; /* RW: Memory address auto increment, 0=disable, 1=enable */
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unsigned short IoAutoInc:1; /* RW: I/O address auto increment, 0=disable, 1=enable */
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unsigned short DiagnosticMode:1; /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
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unsigned short IsaPacingTimer:12; /* R: ISA access pacing timer: count of core cycles stolen */
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} DSP_HBRIDGE_CONTROL;
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/* DSP register indexes used with the configuration register address (index) register */
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#define DSP_UartCfg1Index 0x0003 /* UART config register 1 */
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#define DSP_UartCfg2Index 0x0004 /* UART config register 2 */
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#define DSP_HBridgeCfg1Index 0x0007 /* HBridge config register 1 */
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#define DSP_HBridgeCfg2Index 0x0008 /* HBridge config register 2 */
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#define DSP_BusMasterCfg1Index 0x0009 /* ISA bus master config register 1 */
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#define DSP_BusMasterCfg2Index 0x000A /* ISA bus master config register 2 */
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#define DSP_IsaProtCfgIndex 0x000F /* ISA protocol control register */
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#define DSP_PowerMgCfgIndex 0x0010 /* Low poser suspend/resume enable */
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#define DSP_HBusTimerCfgIndex 0x0011 /* HBUS timer load value */
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typedef struct {
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unsigned char IrqActiveLow:1; /* RW: IRQ active high or low: 0=high, 1=low */
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unsigned char IrqPulse:1; /* RW: IRQ pulse or level: 0=level, 1=pulse */
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unsigned char Irq:3; /* RW: IRQ selection */
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unsigned char BaseIO:2; /* RW: Base I/O selection */
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unsigned char Reserved:1; /* 0: Reserved */
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} DSP_UART_CFG_1;
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typedef struct {
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unsigned char Enable:1; /* RW: Enable I/O and IRQ: 0=false, 1=true */
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unsigned char Reserved:7; /* 0: Reserved */
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} DSP_UART_CFG_2;
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typedef struct {
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unsigned char IrqActiveLow:1; /* RW: IRQ active high=0 or low=1 */
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unsigned char IrqPulse:1; /* RW: IRQ pulse=1 or level=0 */
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unsigned char Irq:3; /* RW: IRQ selection */
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unsigned char AccessMode:1; /* RW: 16-bit register access method 0=byte, 1=word */
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unsigned char Reserved:2; /* 0: Reserved */
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} DSP_HBRIDGE_CFG_1;
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typedef struct {
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unsigned char Enable:1; /* RW: enable I/O and IRQ: 0=false, 1=true */
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unsigned char Reserved:7; /* 0: Reserved */
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} DSP_HBRIDGE_CFG_2;
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typedef struct {
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unsigned char Dma:3; /* RW: DMA channel selection */
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unsigned char NumTransfers:2; /* RW: Maximum # of transfers once being granted the ISA bus */
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unsigned char ReRequest:2; /* RW: Minimum delay between releasing the ISA bus and requesting it again */
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unsigned char MEMCS16:1; /* RW: ISA signal MEMCS16: 0=disabled, 1=enabled */
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} DSP_BUSMASTER_CFG_1;
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typedef struct {
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unsigned char IsaMemCmdWidth:2; /* RW: ISA memory command width */
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unsigned char Reserved:6; /* 0: Reserved */
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} DSP_BUSMASTER_CFG_2;
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typedef struct {
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unsigned char GateIOCHRDY:1; /* RW: Enable IOCHRDY gating: 0=false, 1=true */
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unsigned char Reserved:7; /* 0: Reserved */
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} DSP_ISA_PROT_CFG;
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typedef struct {
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unsigned char Enable:1; /* RW: Enable low power suspend/resume 0=false, 1=true */
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unsigned char Reserved:7; /* 0: Reserved */
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} DSP_POWER_MGMT_CFG;
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typedef struct {
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unsigned char LoadValue:8; /* RW: HBUS timer load value */
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} DSP_HBUS_TIMER_CFG;
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/* DSP registers that exist in MSA I/O space */
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#define DSP_ChipID 0x80000000
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#define DSP_MspBootDomain 0x80000580
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#define DSP_LBusTimeoutDisable 0x80000580
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#define DSP_ClockControl_1 0x8000058A
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#define DSP_ClockControl_2 0x8000058C
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#define DSP_ChipReset 0x80000588
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#define DSP_GpioModeControl_15_8 0x80000082
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#define DSP_GpioDriverEnable_15_8 0x80000076
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#define DSP_GpioOutputData_15_8 0x80000072
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typedef struct {
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unsigned short NMI:1; /* RW: non maskable interrupt */
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unsigned short Halt:1; /* RW: Halt MSP clock */
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unsigned short ResetCore:1; /* RW: Reset MSP core interface */
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unsigned short Reserved:13; /* 0: Reserved */
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} DSP_BOOT_DOMAIN;
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typedef struct {
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unsigned short DisableTimeout:1; /* RW: Disable LBus timeout */
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unsigned short Reserved:15; /* 0: Reserved */
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} DSP_LBUS_TIMEOUT_DISABLE;
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typedef struct {
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unsigned short Memory:1; /* RW: Reset memory interface */
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unsigned short SerialPort1:1; /* RW: Reset serial port 1 interface */
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unsigned short SerialPort2:1; /* RW: Reset serial port 2 interface */
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unsigned short SerialPort3:1; /* RW: Reset serial port 3 interface */
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unsigned short Gpio:1; /* RW: Reset GPIO interface */
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unsigned short Dma:1; /* RW: Reset DMA interface */
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unsigned short SoundBlaster:1; /* RW: Reset soundblaster interface */
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unsigned short Uart:1; /* RW: Reset UART interface */
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unsigned short Midi:1; /* RW: Reset MIDI interface */
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unsigned short IsaMaster:1; /* RW: Reset ISA master interface */
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unsigned short Reserved:6; /* 0: Reserved */
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} DSP_CHIP_RESET;
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typedef struct {
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unsigned short N_Divisor:6; /* RW: (N) PLL output clock divisor */
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unsigned short Reserved1:2; /* 0: reserved */
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unsigned short M_Multiplier:6; /* RW: (M) PLL feedback clock multiplier */
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unsigned short Reserved2:2; /* 0: reserved */
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} DSP_CLOCK_CONTROL_1;
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typedef struct {
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unsigned short PllBypass:1; /* RW: PLL Bypass */
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unsigned short Reserved:15; /* 0: Reserved */
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} DSP_CLOCK_CONTROL_2;
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typedef struct {
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unsigned short Latch8:1;
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unsigned short Latch9:1;
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unsigned short Latch10:1;
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unsigned short Latch11:1;
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unsigned short Latch12:1;
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unsigned short Latch13:1;
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unsigned short Latch14:1;
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unsigned short Latch15:1;
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unsigned short Mask8:1;
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unsigned short Mask9:1;
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unsigned short Mask10:1;
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unsigned short Mask11:1;
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unsigned short Mask12:1;
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unsigned short Mask13:1;
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unsigned short Mask14:1;
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unsigned short Mask15:1;
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} DSP_GPIO_OUTPUT_DATA_15_8;
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typedef struct {
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unsigned short Enable8:1;
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unsigned short Enable9:1;
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unsigned short Enable10:1;
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unsigned short Enable11:1;
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unsigned short Enable12:1;
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unsigned short Enable13:1;
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unsigned short Enable14:1;
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unsigned short Enable15:1;
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unsigned short Mask8:1;
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unsigned short Mask9:1;
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unsigned short Mask10:1;
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unsigned short Mask11:1;
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unsigned short Mask12:1;
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unsigned short Mask13:1;
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unsigned short Mask14:1;
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unsigned short Mask15:1;
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} DSP_GPIO_DRIVER_ENABLE_15_8;
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typedef struct {
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unsigned short GpioMode8:2;
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unsigned short GpioMode9:2;
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unsigned short GpioMode10:2;
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unsigned short GpioMode11:2;
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unsigned short GpioMode12:2;
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unsigned short GpioMode13:2;
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unsigned short GpioMode14:2;
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unsigned short GpioMode15:2;
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} DSP_GPIO_MODE_15_8;
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/* Component masks that are defined in dspmgr.h */
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#define MW_ADC_MASK 0x0001
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#define MW_AIC2_MASK 0x0006
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#define MW_MIDI_MASK 0x0008
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#define MW_CDDAC_MASK 0x8001
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#define MW_AIC1_MASK 0xE006
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#define MW_UART_MASK 0xE00A
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#define MW_ACI_MASK 0xE00B
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/*
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* Definition of 3780i configuration structure. Unless otherwise stated,
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* these values are provided as input to the 3780i support layer. At present,
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* the only values maintained by the 3780i support layer are the saved UART
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* registers.
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*/
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typedef struct _DSP_3780I_CONFIG_SETTINGS {
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/* Location of base configuration register */
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unsigned short usBaseConfigIO;
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/* Enables for various DSP components */
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int bDSPEnabled;
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int bModemEnabled;
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int bInterruptClaimed;
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/* IRQ, DMA, and Base I/O addresses for various DSP components */
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unsigned short usDspIrq;
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unsigned short usDspDma;
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unsigned short usDspBaseIO;
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unsigned short usUartIrq;
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unsigned short usUartBaseIO;
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/* IRQ modes for various DSP components */
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int bDspIrqActiveLow;
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int bUartIrqActiveLow;
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int bDspIrqPulse;
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int bUartIrqPulse;
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/* Card abilities */
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unsigned uIps;
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unsigned uDStoreSize;
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unsigned uIStoreSize;
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unsigned uDmaBandwidth;
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/* Adapter specific 3780i settings */
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unsigned short usNumTransfers;
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unsigned short usReRequest;
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int bEnableMEMCS16;
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unsigned short usIsaMemCmdWidth;
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int bGateIOCHRDY;
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int bEnablePwrMgmt;
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unsigned short usHBusTimerLoadValue;
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int bDisableLBusTimeout;
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unsigned short usN_Divisor;
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unsigned short usM_Multiplier;
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int bPllBypass;
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unsigned short usChipletEnable; /* Used with the chip reset register to enable specific chiplets */
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/* Saved UART registers. These are maintained by the 3780i support layer. */
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int bUartSaved; /* True after a successful save of the UART registers */
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unsigned char ucIER; /* Interrupt enable register */
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unsigned char ucFCR; /* FIFO control register */
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unsigned char ucLCR; /* Line control register */
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unsigned char ucMCR; /* Modem control register */
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unsigned char ucSCR; /* Scratch register */
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unsigned char ucDLL; /* Divisor latch, low byte */
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unsigned char ucDLM; /* Divisor latch, high byte */
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} DSP_3780I_CONFIG_SETTINGS;
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/* 3780i support functions */
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int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
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unsigned short *pIrqMap,
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unsigned short *pDmaMap);
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int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings);
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int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings);
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int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings);
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int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
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unsigned uCount, unsigned long ulDSPAddr);
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int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
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void __user *pvBuffer, unsigned uCount,
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unsigned long ulDSPAddr);
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int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
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unsigned uCount, unsigned long ulDSPAddr);
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int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
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unsigned uCount, unsigned long ulDSPAddr);
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int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
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unsigned uCount, unsigned long ulDSPAddr);
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unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
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unsigned long ulMsaAddr);
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void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
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unsigned long ulMsaAddr, unsigned short usValue);
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int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
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unsigned short *pusIPCSource);
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/* I/O port access macros */
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#define MKWORD(var) (*((unsigned short *)(&var)))
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#define MKBYTE(var) (*((unsigned char *)(&var)))
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#define WriteMsaCfg(addr,value) dsp3780I_WriteMsaCfg(usDspBaseIO,addr,value)
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#define ReadMsaCfg(addr) dsp3780I_ReadMsaCfg(usDspBaseIO,addr)
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#define WriteGenCfg(index,value) dsp3780I_WriteGenCfg(usDspBaseIO,index,value)
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#define ReadGenCfg(index) dsp3780I_ReadGenCfg(usDspBaseIO,index)
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#define InWordDsp(index) inw(usDspBaseIO+index)
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#define InByteDsp(index) inb(usDspBaseIO+index)
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#define OutWordDsp(index,value) outw(value,usDspBaseIO+index)
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#define OutByteDsp(index,value) outb(value,usDspBaseIO+index)
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#endif
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