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Intel processors starting with the Core Duo support support processor native C-state using the MWAIT instruction. Refer: Intel Architecture Software Developer's Manual http://www.intel.com/design/Pentium4/manuals/253668.htm Platform firmware exports the support for Native C-state to OS using ACPI _PDC and _CST methods. Refer: Intel Processor Vendor-Specific ACPI: Interface Specification http://www.intel.com/technology/iapc/acpi/downloads/302223.htm With Processor Native C-state, we use 'MWAIT' instruction on the processor to enter different C-states (C1, C2, C3). We won't use the special IO ports to enter C-state and no SMM mode etc required to enter C-state. Overall this will mean better C-state support. One major advantage of using MWAIT for all C-states is, with this and "treat interrupt as break event" feature of MWAIT, we can now get accurate timing for the time spent in C1, C2, .. states. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Len Brown <len.brown@intel.com>
34 lines
935 B
C
34 lines
935 B
C
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/* _PDC bit definition for Intel processors */
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#ifndef __PDC_INTEL_H__
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#define __PDC_INTEL_H__
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#define ACPI_PDC_P_FFH (0x0001)
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#define ACPI_PDC_C_C1_HALT (0x0002)
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#define ACPI_PDC_T_FFH (0x0004)
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#define ACPI_PDC_SMP_C1PT (0x0008)
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#define ACPI_PDC_SMP_C2C3 (0x0010)
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#define ACPI_PDC_SMP_P_SWCOORD (0x0020)
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#define ACPI_PDC_SMP_C_SWCOORD (0x0040)
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#define ACPI_PDC_SMP_T_SWCOORD (0x0080)
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#define ACPI_PDC_C_C1_FFH (0x0100)
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#define ACPI_PDC_C_C2C3_FFH (0x0200)
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#define ACPI_PDC_EST_CAPABILITY_SMP (ACPI_PDC_SMP_C1PT | \
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ACPI_PDC_C_C1_HALT | \
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ACPI_PDC_P_FFH)
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#define ACPI_PDC_EST_CAPABILITY_SWSMP (ACPI_PDC_SMP_C1PT | \
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ACPI_PDC_C_C1_HALT | \
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ACPI_PDC_SMP_P_SWCOORD | \
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ACPI_PDC_P_FFH)
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#define ACPI_PDC_C_CAPABILITY_SMP (ACPI_PDC_SMP_C2C3 | \
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ACPI_PDC_SMP_C1PT | \
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ACPI_PDC_C_C1_HALT | \
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ACPI_PDC_C_C1_FFH | \
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ACPI_PDC_C_C2C3_FFH)
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#endif /* __PDC_INTEL_H__ */
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