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This patch adds documentation for the uncore PMUs on HiSilicon SoC. Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by: Anurup M <anurup.m@huawei.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
54 lines
2.4 KiB
Plaintext
54 lines
2.4 KiB
Plaintext
HiSilicon SoC uncore Performance Monitoring Unit (PMU)
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======================================================
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The HiSilicon SoC chip includes various independent system device PMUs
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such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
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independent and have hardware logic to gather statistics and performance
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information.
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The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
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(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
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called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
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two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
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HiSilicon SoC uncore PMU driver
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---------------------------------------
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Each device PMU has separate registers for event counting, control and
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interrupt, and the PMU driver shall register perf PMU drivers like L3C,
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HHA and DDRC etc. The available events and configuration options shall
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be described in the sysfs, see :
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/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
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The "perf list" command shall list the available events from sysfs.
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Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
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name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
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where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
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module.
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e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
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SCCL ID #3.
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e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
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SCCL ID #1.
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The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
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ID used to count the uncore PMU event.
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Example usage of perf:
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$# perf list
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hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
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$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
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The current driver does not support sampling. So "perf record" is unsupported.
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Also attach to a task is unsupported as the events are all uncore.
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Note: Please contact the maintainer for a complete list of events supported for
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the PMU devices in the SoC and its information if needed.
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