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d919501fef
This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by: Tero Kristo <t-kristo@ti.com>
80 lines
1.8 KiB
Plaintext
80 lines
1.8 KiB
Plaintext
OMAP Control Module bindings
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Control Module contains miscellaneous features under it based on SoC type.
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Pincontrol is one common feature, and it has a specialized support
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described in [1]. Typically some clock nodes are also under control module.
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Syscon is used to share register level access to drivers external to
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control module driver itself.
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See [2] for documentation about clock/clockdomain nodes.
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[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
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[2] Documentation/devicetree/bindings/clock/ti/*
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Required properties:
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- compatible: Must be one of:
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"ti,am3-scm"
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"ti,am4-scm"
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"ti,dm814-scrm"
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"ti,dm816-scrm"
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"ti,omap2-scm"
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"ti,omap3-scm"
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"ti,omap4-scm-core"
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"ti,omap4-scm-padconf-core"
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"ti,omap5-scm-core"
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"ti,omap5-scm-padconf-core"
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"ti,dra7-scm-core"
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- reg: Contains Control Module register address range
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(base address and length)
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Optional properties:
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- clocks: clocks for this module
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- clockdomains: clockdomains for this module
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Examples:
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scm: scm@2000 {
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compatible = "ti,omap3-scm", "simple-bus";
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reg = <0x2000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2000 0x2000>;
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omap3_pmx_core: pinmux@30 {
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compatible = "ti,omap3-padconf",
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"pinctrl-single";
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reg = <0x30 0x230>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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scm_conf: scm_conf@270 {
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compatible = "syscon";
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reg = <0x270 0x330>;
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#address-cells = <1>;
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#size-cells = <1>;
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scm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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scm_clockdomains: clockdomains {
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};
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}
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&scm_clocks {
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mcbsp5_mux_fck: mcbsp5_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&core_96m_fck>, <&mcbsp_clks>;
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ti,bit-shift = <4>;
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reg = <0x02d8>;
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};
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};
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