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6270068202
This patch adds the reset controller functionality for Peripheral PHYs to the Arria10 System Resource Chip. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
/*
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* Copyright Intel Corporation (C) 2017. All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Reset driver for Altera Arria10 MAX5 System Resource Chip
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*
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* Adapted from reset-socfpga.c
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*/
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#include <linux/err.h>
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#include <linux/mfd/altera-a10sr.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/reset/altr,rst-mgr-a10sr.h>
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struct a10sr_reset {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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};
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static inline struct a10sr_reset *to_a10sr_rst(struct reset_controller_dev *rc)
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{
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return container_of(rc, struct a10sr_reset, rcdev);
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}
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static inline int a10sr_reset_shift(unsigned long id)
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{
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switch (id) {
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case A10SR_RESET_ENET_HPS:
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return 1;
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case A10SR_RESET_PCIE:
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case A10SR_RESET_FILE:
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case A10SR_RESET_BQSPI:
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case A10SR_RESET_USB:
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return id + 11;
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default:
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return -EINVAL;
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}
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}
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static int a10sr_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct a10sr_reset *a10r = to_a10sr_rst(rcdev);
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int offset = a10sr_reset_shift(id);
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u8 mask = ALTR_A10SR_REG_BIT_MASK(offset);
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int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset);
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return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask);
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}
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static int a10sr_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return a10sr_reset_update(rcdev, id, true);
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}
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static int a10sr_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return a10sr_reset_update(rcdev, id, false);
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}
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static int a10sr_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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int ret;
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struct a10sr_reset *a10r = to_a10sr_rst(rcdev);
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int offset = a10sr_reset_shift(id);
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u8 mask = ALTR_A10SR_REG_BIT_MASK(offset);
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int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset);
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unsigned int value;
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ret = regmap_read(a10r->regmap, index, &value);
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if (ret < 0)
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return ret;
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return !!(value & mask);
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}
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static const struct reset_control_ops a10sr_reset_ops = {
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.assert = a10sr_reset_assert,
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.deassert = a10sr_reset_deassert,
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.status = a10sr_reset_status,
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};
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static int a10sr_reset_probe(struct platform_device *pdev)
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{
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struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
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struct a10sr_reset *a10r;
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a10r = devm_kzalloc(&pdev->dev, sizeof(struct a10sr_reset),
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GFP_KERNEL);
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if (!a10r)
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return -ENOMEM;
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a10r->rcdev.owner = THIS_MODULE;
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a10r->rcdev.nr_resets = A10SR_RESET_NUM;
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a10r->rcdev.ops = &a10sr_reset_ops;
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a10r->rcdev.of_node = pdev->dev.of_node;
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a10r->regmap = a10sr->regmap;
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platform_set_drvdata(pdev, a10r);
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return devm_reset_controller_register(&pdev->dev, &a10r->rcdev);
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}
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static const struct of_device_id a10sr_reset_of_match[] = {
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{ .compatible = "altr,a10sr-reset" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, a10sr_reset_of_match);
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static struct platform_driver a10sr_reset_driver = {
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.probe = a10sr_reset_probe,
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.driver = {
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.name = "altr_a10sr_reset",
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},
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};
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module_platform_driver(a10sr_reset_driver);
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MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
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MODULE_DESCRIPTION("Altera Arria10 System Resource Reset Controller Driver");
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MODULE_LICENSE("GPL v2");
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