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6445671b00
Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Matt Turner <mattst88@gmail.com>
23 lines
468 B
C
23 lines
468 B
C
/*
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* include/asm-alpha/cache.h
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*/
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#ifndef __ARCH_ALPHA_CACHE_H
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#define __ARCH_ALPHA_CACHE_H
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/* Bytes per L1 (data) cache line. */
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6)
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# define L1_CACHE_BYTES 64
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# define L1_CACHE_SHIFT 6
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#else
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/* Both EV4 and EV5 are write-through, read-allocate,
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direct-mapped, physical.
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*/
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# define L1_CACHE_BYTES 32
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# define L1_CACHE_SHIFT 5
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#endif
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#endif
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