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f422fa558a
The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing
in the ccu-sun50i-h6 driver.
Add this missing clock to the driver.
Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
126 lines
2.9 KiB
C
126 lines
2.9 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*/
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#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
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#define _DT_BINDINGS_CLK_SUN50I_H6_H_
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#define CLK_PLL_PERIPH0 3
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#define CLK_CPUX 21
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#define CLK_APB1 26
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#define CLK_DE 29
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#define CLK_BUS_DE 30
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#define CLK_DEINTERLACE 31
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#define CLK_BUS_DEINTERLACE 32
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#define CLK_GPU 33
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#define CLK_BUS_GPU 34
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#define CLK_CE 35
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#define CLK_BUS_CE 36
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#define CLK_VE 37
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#define CLK_BUS_VE 38
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#define CLK_EMCE 39
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#define CLK_BUS_EMCE 40
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#define CLK_VP9 41
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#define CLK_BUS_VP9 42
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#define CLK_BUS_DMA 43
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#define CLK_BUS_MSGBOX 44
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#define CLK_BUS_SPINLOCK 45
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#define CLK_BUS_HSTIMER 46
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#define CLK_AVS 47
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#define CLK_BUS_DBG 48
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#define CLK_BUS_PSI 49
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#define CLK_BUS_PWM 50
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#define CLK_BUS_IOMMU 51
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#define CLK_MBUS_DMA 53
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#define CLK_MBUS_VE 54
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#define CLK_MBUS_CE 55
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#define CLK_MBUS_TS 56
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#define CLK_MBUS_NAND 57
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#define CLK_MBUS_CSI 58
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#define CLK_MBUS_DEINTERLACE 59
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#define CLK_NAND0 61
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#define CLK_NAND1 62
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#define CLK_BUS_NAND 63
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#define CLK_MMC0 64
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#define CLK_MMC1 65
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#define CLK_MMC2 66
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#define CLK_BUS_MMC0 67
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#define CLK_BUS_MMC1 68
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#define CLK_BUS_MMC2 69
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#define CLK_BUS_UART0 70
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#define CLK_BUS_UART1 71
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#define CLK_BUS_UART2 72
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#define CLK_BUS_UART3 73
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#define CLK_BUS_I2C0 74
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#define CLK_BUS_I2C1 75
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#define CLK_BUS_I2C2 76
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#define CLK_BUS_I2C3 77
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#define CLK_BUS_SCR0 78
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#define CLK_BUS_SCR1 79
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#define CLK_SPI0 80
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#define CLK_SPI1 81
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#define CLK_BUS_SPI0 82
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#define CLK_BUS_SPI1 83
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#define CLK_BUS_EMAC 84
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#define CLK_TS 85
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#define CLK_BUS_TS 86
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#define CLK_IR_TX 87
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#define CLK_BUS_IR_TX 88
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#define CLK_BUS_THS 89
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#define CLK_I2S3 90
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#define CLK_I2S0 91
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#define CLK_I2S1 92
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#define CLK_I2S2 93
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#define CLK_BUS_I2S0 94
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#define CLK_BUS_I2S1 95
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#define CLK_BUS_I2S2 96
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#define CLK_BUS_I2S3 97
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#define CLK_SPDIF 98
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#define CLK_BUS_SPDIF 99
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#define CLK_DMIC 100
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#define CLK_BUS_DMIC 101
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#define CLK_AUDIO_HUB 102
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#define CLK_BUS_AUDIO_HUB 103
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#define CLK_USB_OHCI0 104
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#define CLK_USB_PHY0 105
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#define CLK_USB_PHY1 106
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#define CLK_USB_OHCI3 107
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#define CLK_USB_PHY3 108
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#define CLK_USB_HSIC_12M 109
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#define CLK_USB_HSIC 110
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#define CLK_BUS_OHCI0 111
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#define CLK_BUS_OHCI3 112
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#define CLK_BUS_EHCI0 113
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#define CLK_BUS_XHCI 114
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#define CLK_BUS_EHCI3 115
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#define CLK_BUS_OTG 116
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#define CLK_PCIE_REF_100M 117
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#define CLK_PCIE_REF 118
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#define CLK_PCIE_REF_OUT 119
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#define CLK_PCIE_MAXI 120
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#define CLK_PCIE_AUX 121
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#define CLK_BUS_PCIE 122
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#define CLK_HDMI 123
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#define CLK_HDMI_SLOW 124
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#define CLK_HDMI_CEC 125
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#define CLK_BUS_HDMI 126
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#define CLK_BUS_TCON_TOP 127
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#define CLK_TCON_LCD0 128
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#define CLK_BUS_TCON_LCD0 129
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#define CLK_TCON_TV0 130
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#define CLK_BUS_TCON_TV0 131
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#define CLK_CSI_CCI 132
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#define CLK_CSI_TOP 133
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#define CLK_CSI_MCLK 134
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#define CLK_BUS_CSI 135
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#define CLK_HDCP 136
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#define CLK_BUS_HDCP 137
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#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
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