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6ad7cb7122
i.MX8QXP contains Hifi4 DSP. There are four clocks associated with DSP: * dsp_lpcg_core_clk * dsp_lpcg_ipg_clk * dsp_lpcg_adb_aclk * ocram_lpcg_ipg_clk Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
294 lines
9.6 KiB
C
294 lines
9.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX_H
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#define __DT_BINDINGS_CLOCK_IMX_H
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/* SCU Clocks */
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#define IMX_CLK_DUMMY 0
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/* CPU */
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#define IMX_A35_CLK 1
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/* LSIO SS */
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#define IMX_LSIO_MEM_CLK 2
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#define IMX_LSIO_BUS_CLK 3
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#define IMX_LSIO_PWM0_CLK 10
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#define IMX_LSIO_PWM1_CLK 11
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#define IMX_LSIO_PWM2_CLK 12
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#define IMX_LSIO_PWM3_CLK 13
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#define IMX_LSIO_PWM4_CLK 14
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#define IMX_LSIO_PWM5_CLK 15
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#define IMX_LSIO_PWM6_CLK 16
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#define IMX_LSIO_PWM7_CLK 17
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#define IMX_LSIO_GPT0_CLK 18
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#define IMX_LSIO_GPT1_CLK 19
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#define IMX_LSIO_GPT2_CLK 20
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#define IMX_LSIO_GPT3_CLK 21
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#define IMX_LSIO_GPT4_CLK 22
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#define IMX_LSIO_FSPI0_CLK 23
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#define IMX_LSIO_FSPI1_CLK 24
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/* Connectivity SS */
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#define IMX_CONN_AXI_CLK_ROOT 30
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#define IMX_CONN_AHB_CLK_ROOT 31
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#define IMX_CONN_IPG_CLK_ROOT 32
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#define IMX_CONN_SDHC0_CLK 40
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#define IMX_CONN_SDHC1_CLK 41
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#define IMX_CONN_SDHC2_CLK 42
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#define IMX_CONN_ENET0_ROOT_CLK 43
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#define IMX_CONN_ENET0_BYPASS_CLK 44
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#define IMX_CONN_ENET0_RGMII_CLK 45
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#define IMX_CONN_ENET1_ROOT_CLK 46
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#define IMX_CONN_ENET1_BYPASS_CLK 47
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#define IMX_CONN_ENET1_RGMII_CLK 48
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#define IMX_CONN_GPMI_BCH_IO_CLK 49
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#define IMX_CONN_GPMI_BCH_CLK 50
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#define IMX_CONN_USB2_ACLK 51
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#define IMX_CONN_USB2_BUS_CLK 52
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#define IMX_CONN_USB2_LPM_CLK 53
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/* HSIO SS */
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#define IMX_HSIO_AXI_CLK 60
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#define IMX_HSIO_PER_CLK 61
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/* Display controller SS */
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#define IMX_DC_AXI_EXT_CLK 70
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#define IMX_DC_AXI_INT_CLK 71
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#define IMX_DC_CFG_CLK 72
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#define IMX_DC0_PLL0_CLK 80
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#define IMX_DC0_PLL1_CLK 81
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#define IMX_DC0_DISP0_CLK 82
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#define IMX_DC0_DISP1_CLK 83
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/* MIPI-LVDS SS */
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#define IMX_MIPI_IPG_CLK 90
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#define IMX_MIPI0_PIXEL_CLK 100
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#define IMX_MIPI0_BYPASS_CLK 101
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#define IMX_MIPI0_LVDS_PIXEL_CLK 102
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#define IMX_MIPI0_LVDS_BYPASS_CLK 103
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#define IMX_MIPI0_LVDS_PHY_CLK 104
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#define IMX_MIPI0_I2C0_CLK 105
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#define IMX_MIPI0_I2C1_CLK 106
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#define IMX_MIPI0_PWM0_CLK 107
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#define IMX_MIPI1_PIXEL_CLK 108
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#define IMX_MIPI1_BYPASS_CLK 109
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#define IMX_MIPI1_LVDS_PIXEL_CLK 110
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#define IMX_MIPI1_LVDS_BYPASS_CLK 111
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#define IMX_MIPI1_LVDS_PHY_CLK 112
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#define IMX_MIPI1_I2C0_CLK 113
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#define IMX_MIPI1_I2C1_CLK 114
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#define IMX_MIPI1_PWM0_CLK 115
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/* IMG SS */
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#define IMX_IMG_AXI_CLK 120
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#define IMX_IMG_IPG_CLK 121
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#define IMX_IMG_PXL_CLK 122
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/* MIPI-CSI SS */
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#define IMX_CSI0_CORE_CLK 130
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#define IMX_CSI0_ESC_CLK 131
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#define IMX_CSI0_PWM0_CLK 132
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#define IMX_CSI0_I2C0_CLK 133
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/* PARALLER CSI SS */
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#define IMX_PARALLEL_CSI_DPLL_CLK 140
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#define IMX_PARALLEL_CSI_PIXEL_CLK 141
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#define IMX_PARALLEL_CSI_MCLK_CLK 142
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/* VPU SS */
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#define IMX_VPU_ENC_CLK 150
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#define IMX_VPU_DEC_CLK 151
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/* GPU SS */
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#define IMX_GPU0_CORE_CLK 160
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#define IMX_GPU0_SHADER_CLK 161
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/* ADMA SS */
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#define IMX_ADMA_IPG_CLK_ROOT 165
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#define IMX_ADMA_UART0_CLK 170
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#define IMX_ADMA_UART1_CLK 171
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#define IMX_ADMA_UART2_CLK 172
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#define IMX_ADMA_UART3_CLK 173
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#define IMX_ADMA_SPI0_CLK 174
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#define IMX_ADMA_SPI1_CLK 175
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#define IMX_ADMA_SPI2_CLK 176
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#define IMX_ADMA_SPI3_CLK 177
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#define IMX_ADMA_CAN0_CLK 178
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#define IMX_ADMA_CAN1_CLK 179
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#define IMX_ADMA_CAN2_CLK 180
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#define IMX_ADMA_I2C0_CLK 181
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#define IMX_ADMA_I2C1_CLK 182
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#define IMX_ADMA_I2C2_CLK 183
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#define IMX_ADMA_I2C3_CLK 184
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#define IMX_ADMA_FTM0_CLK 185
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#define IMX_ADMA_FTM1_CLK 186
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#define IMX_ADMA_ADC0_CLK 187
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#define IMX_ADMA_PWM_CLK 188
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#define IMX_ADMA_LCD_CLK 189
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#define IMX_SCU_CLK_END 190
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/* LPCG clocks */
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/* LSIO SS LPCG */
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#define IMX_LSIO_LPCG_PWM0_IPG_CLK 0
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#define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1
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#define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2
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#define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3
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#define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4
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#define IMX_LSIO_LPCG_PWM1_IPG_CLK 5
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#define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6
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#define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7
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#define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8
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#define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9
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#define IMX_LSIO_LPCG_PWM2_IPG_CLK 10
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#define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11
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#define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12
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#define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13
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#define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14
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#define IMX_LSIO_LPCG_PWM3_IPG_CLK 15
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#define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16
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#define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17
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#define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18
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#define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19
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#define IMX_LSIO_LPCG_PWM4_IPG_CLK 20
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#define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21
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#define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22
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#define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23
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#define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24
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#define IMX_LSIO_LPCG_PWM5_IPG_CLK 25
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#define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26
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#define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27
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#define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28
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#define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29
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#define IMX_LSIO_LPCG_PWM6_IPG_CLK 30
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#define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31
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#define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32
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#define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33
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#define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34
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#define IMX_LSIO_LPCG_PWM7_IPG_CLK 35
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#define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36
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#define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37
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#define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38
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#define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39
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#define IMX_LSIO_LPCG_GPT0_IPG_CLK 40
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#define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41
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#define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42
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#define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43
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#define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44
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#define IMX_LSIO_LPCG_GPT1_IPG_CLK 45
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#define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46
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#define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47
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#define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48
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#define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49
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#define IMX_LSIO_LPCG_GPT2_IPG_CLK 50
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#define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51
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#define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52
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#define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53
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#define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54
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#define IMX_LSIO_LPCG_GPT3_IPG_CLK 55
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#define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56
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#define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57
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#define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58
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#define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59
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#define IMX_LSIO_LPCG_GPT4_IPG_CLK 60
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#define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61
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#define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62
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#define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63
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#define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64
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#define IMX_LSIO_LPCG_FSPI0_HCLK 65
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#define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66
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#define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67
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#define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68
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#define IMX_LSIO_LPCG_FSPI1_HCLK 69
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#define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70
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#define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71
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#define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72
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#define IMX_LSIO_LPCG_CLK_END 73
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/* Connectivity SS LPCG */
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#define IMX_CONN_LPCG_SDHC0_IPG_CLK 0
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#define IMX_CONN_LPCG_SDHC0_PER_CLK 1
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#define IMX_CONN_LPCG_SDHC0_HCLK 2
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#define IMX_CONN_LPCG_SDHC1_IPG_CLK 3
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#define IMX_CONN_LPCG_SDHC1_PER_CLK 4
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#define IMX_CONN_LPCG_SDHC1_HCLK 5
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#define IMX_CONN_LPCG_SDHC2_IPG_CLK 6
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#define IMX_CONN_LPCG_SDHC2_PER_CLK 7
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#define IMX_CONN_LPCG_SDHC2_HCLK 8
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#define IMX_CONN_LPCG_GPMI_APB_CLK 9
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#define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10
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#define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11
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#define IMX_CONN_LPCG_GPMI_BCH_CLK 12
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#define IMX_CONN_LPCG_APBHDMA_CLK 13
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#define IMX_CONN_LPCG_ENET0_ROOT_CLK 14
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#define IMX_CONN_LPCG_ENET0_TX_CLK 15
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#define IMX_CONN_LPCG_ENET0_AHB_CLK 16
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#define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17
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#define IMX_CONN_LPCG_ENET0_IPG_CLK 18
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#define IMX_CONN_LPCG_ENET1_ROOT_CLK 19
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#define IMX_CONN_LPCG_ENET1_TX_CLK 20
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#define IMX_CONN_LPCG_ENET1_AHB_CLK 21
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#define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22
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#define IMX_CONN_LPCG_ENET1_IPG_CLK 23
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#define IMX_CONN_LPCG_CLK_END 24
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/* ADMA SS LPCG */
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#define IMX_ADMA_LPCG_UART0_IPG_CLK 0
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#define IMX_ADMA_LPCG_UART0_BAUD_CLK 1
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#define IMX_ADMA_LPCG_UART1_IPG_CLK 2
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#define IMX_ADMA_LPCG_UART1_BAUD_CLK 3
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#define IMX_ADMA_LPCG_UART2_IPG_CLK 4
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#define IMX_ADMA_LPCG_UART2_BAUD_CLK 5
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#define IMX_ADMA_LPCG_UART3_IPG_CLK 6
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#define IMX_ADMA_LPCG_UART3_BAUD_CLK 7
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#define IMX_ADMA_LPCG_SPI0_IPG_CLK 8
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#define IMX_ADMA_LPCG_SPI1_IPG_CLK 9
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#define IMX_ADMA_LPCG_SPI2_IPG_CLK 10
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#define IMX_ADMA_LPCG_SPI3_IPG_CLK 11
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#define IMX_ADMA_LPCG_SPI0_CLK 12
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#define IMX_ADMA_LPCG_SPI1_CLK 13
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#define IMX_ADMA_LPCG_SPI2_CLK 14
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#define IMX_ADMA_LPCG_SPI3_CLK 15
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#define IMX_ADMA_LPCG_CAN0_IPG_CLK 16
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#define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17
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#define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18
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#define IMX_ADMA_LPCG_CAN1_IPG_CLK 19
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#define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20
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#define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21
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#define IMX_ADMA_LPCG_CAN2_IPG_CLK 22
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#define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23
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#define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24
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#define IMX_ADMA_LPCG_I2C0_CLK 25
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#define IMX_ADMA_LPCG_I2C1_CLK 26
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#define IMX_ADMA_LPCG_I2C2_CLK 27
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#define IMX_ADMA_LPCG_I2C3_CLK 28
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#define IMX_ADMA_LPCG_I2C0_IPG_CLK 29
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#define IMX_ADMA_LPCG_I2C1_IPG_CLK 30
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#define IMX_ADMA_LPCG_I2C2_IPG_CLK 31
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#define IMX_ADMA_LPCG_I2C3_IPG_CLK 32
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#define IMX_ADMA_LPCG_FTM0_CLK 33
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#define IMX_ADMA_LPCG_FTM1_CLK 34
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#define IMX_ADMA_LPCG_FTM0_IPG_CLK 35
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#define IMX_ADMA_LPCG_FTM1_IPG_CLK 36
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#define IMX_ADMA_LPCG_PWM_HI_CLK 37
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#define IMX_ADMA_LPCG_PWM_IPG_CLK 38
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#define IMX_ADMA_LPCG_LCD_PIX_CLK 39
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#define IMX_ADMA_LPCG_LCD_APB_CLK 40
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#define IMX_ADMA_LPCG_DSP_ADB_CLK 41
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#define IMX_ADMA_LPCG_DSP_IPG_CLK 42
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#define IMX_ADMA_LPCG_DSP_CORE_CLK 43
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#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
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#define IMX_ADMA_LPCG_CLK_END 45
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#endif /* __DT_BINDINGS_CLOCK_IMX_H */
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