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b97021f855
The Documentation/memory-barriers.txt document requires that atomic operations that return a value act as a memory barrier both before and after the actual atomic operation. Our current implementation doesn't guarantee this. More specifically, while a load following the isync can not be issued before stwcx. has completed, that completion doesn't architecturally means that the result of stwcx. is visible to other processors (or any previous stores for that matter) (typically, the other processors L1 caches can still hold the old value). This has caused an actual crash in RCU torture testing on Power 7 This fixes it by changing those atomic ops to use new macros instead of RELEASE/ACQUIRE barriers, called ATOMIC_ENTRY and ATMOIC_EXIT barriers, which are then defined respectively to lwsync and sync. I haven't had a chance to measure the performance impact (or rather what I measured with kernel compiles is in the noise, I yet have to find a more precise benchmark) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
122 lines
2.9 KiB
C
122 lines
2.9 KiB
C
#ifndef _ASM_POWERPC_FUTEX_H
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#define _ASM_POWERPC_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#include <asm/synch.h>
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#include <asm/asm-compat.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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__asm__ __volatile ( \
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PPC_ATOMIC_ENTRY_BARRIER \
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"1: lwarx %0,0,%2\n" \
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insn \
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PPC405_ERR77(0, %2) \
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"2: stwcx. %1,0,%2\n" \
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"bne- 1b\n" \
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PPC_ATOMIC_EXIT_BARRIER \
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"li %1,0\n" \
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"3: .section .fixup,\"ax\"\n" \
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"4: li %1,%3\n" \
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"b 3b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n" \
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".align 3\n" \
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PPC_LONG "1b,4b,2b,4b\n" \
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".previous" \
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: "=&r" (oldval), "=&r" (ret) \
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: "b" (uaddr), "i" (-EFAULT), "r" (oparg) \
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: "cr0", "memory")
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static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
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{
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int op = (encoded_op >> 28) & 7;
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int cmp = (encoded_op >> 24) & 15;
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int oparg = (encoded_op << 8) >> 20;
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int cmparg = (encoded_op << 20) >> 20;
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int oldval = 0, ret;
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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oparg = 1 << oparg;
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if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mr %1,%4\n", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add %1,%0,%4\n", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("or %1,%0,%4\n", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("andc %1,%0,%4\n", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("xor %1,%0,%4\n", ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret) {
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switch (cmp) {
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case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
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case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
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case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
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case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
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case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
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case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
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default: ret = -ENOSYS;
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}
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}
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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int ret = 0;
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u32 prev;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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__asm__ __volatile__ (
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %1,0,%3 # futex_atomic_cmpxchg_inatomic\n\
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cmpw 0,%1,%4\n\
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bne- 3f\n"
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PPC405_ERR77(0,%3)
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"2: stwcx. %5,0,%3\n\
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bne- 1b\n"
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PPC_ATOMIC_EXIT_BARRIER
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"3: .section .fixup,\"ax\"\n\
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4: li %0,%6\n\
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b 3b\n\
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.previous\n\
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.section __ex_table,\"a\"\n\
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.align 3\n\
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" PPC_LONG "1b,4b,2b,4b\n\
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.previous" \
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: "+r" (ret), "=&r" (prev), "+m" (*uaddr)
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: "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
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: "cc", "memory");
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*uval = prev;
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return ret;
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_FUTEX_H */
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