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436d42c61c
Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the samsung include directories Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Jeff Garzik <jgarzik@pobox.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: "Wolfram Sang (embedded platforms)" <w.sang@pengutronix.de> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Bryan Wu <bryan.wu@canonical.com> Cc: Richard Purdie <rpurdie@rpsys.net> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Chris Ball <cjb@laptop.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Felipe Balbi <balbi@ti.com> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Sangbeom Kim <sbkim73@samsung.com> Cc: Liam Girdwood <lrg@ti.com> Cc: linux-samsung-soc@vger.kernel.org
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/* linux/arch/arm/mach-s3c64xx/setup-ide.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S3C64XX setup information for IDE
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <plat/gpio-cfg.h>
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#include <linux/platform_data/ata-samsung_cf.h>
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void s3c64xx_ide_setup_gpio(void)
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{
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u32 reg;
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reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
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/* Independent CF interface, CF chip select configuration */
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writel(reg | MEM_SYS_CFG_INDEP_CF |
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MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
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s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
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/* Set XhiDATA[15:0] pins as CF Data[15:0] */
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s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
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/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
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s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
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/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
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s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
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s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
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}
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