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https://github.com/edk2-porting/linux-next.git
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39e688a94b
These ended up causing too many problems on older parts, revert for now.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
98 lines
2.3 KiB
C
98 lines
2.3 KiB
C
/*
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* arch/sh/mm/tlb-sh3.c
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*
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* SH-3 specific TLB operations
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2002 Paul Mundt
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*
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* Released under the terms of the GNU GPL v2.0.
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*/
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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void update_mmu_cache(struct vm_area_struct * vma,
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unsigned long address, pte_t pte)
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{
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unsigned long flags;
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unsigned long pteval;
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unsigned long vpn;
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/* Ptrace may call this routine. */
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if (vma && current->active_mm != vma->vm_mm)
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return;
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#if defined(CONFIG_SH7705_CACHE_32KB)
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{
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struct page *page = pte_page(pte);
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unsigned long pfn = pte_pfn(pte);
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if (pfn_valid(pfn) && !test_bit(PG_mapped, &page->flags)) {
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unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
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__flush_wback_region((void *)P1SEGADDR(phys),
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PAGE_SIZE);
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__set_bit(PG_mapped, &page->flags);
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}
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}
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#endif
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local_irq_save(flags);
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/* Set PTEH register */
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vpn = (address & MMU_VPN_MASK) | get_asid();
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ctrl_outl(vpn, MMU_PTEH);
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pteval = pte_val(pte);
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/* Set PTEL register */
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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/* conveniently, we want all the software flags to be 0 anyway */
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ctrl_outl(pteval, MMU_PTEL);
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/* Load the TLB */
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asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
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local_irq_restore(flags);
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}
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void local_flush_tlb_one(unsigned long asid, unsigned long page)
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{
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unsigned long addr, data;
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int i, ways = MMU_NTLB_WAYS;
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/*
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* NOTE: PTEH.ASID should be set to this MM
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* _AND_ we need to write ASID to the array.
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*
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* It would be simple if we didn't need to set PTEH.ASID...
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*/
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addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
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data = (page & 0xfffe0000) | asid; /* VALID bit is off */
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if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
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addr |= MMU_PAGE_ASSOC_BIT;
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ways = 1; /* we already know the way .. */
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}
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for (i = 0; i < ways; i++)
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ctrl_outl(data, addr + (i << 8));
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}
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