Thomas Betker 6632d4fdd7 ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1) ... This patch is based on the commit 1a8e41cd67 ("ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register") Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. For Zynq, this fix avoids memory inconsistencies between Gigabit Ethernet controller (GEM) and CPU when DMA_CMA is disabled. Suggested-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2015-07-22 09:37:58 +02:00
..
common.c	ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)	2015-07-22 09:37:58 +02:00
common.h	ARM: SoC: platform support for v4.2	2015-06-26 11:34:35 -07:00
headsmp.S	ARM: v7 setup function should invalidate L1 cache	2015-06-01 11:30:26 +01:00
Kconfig	ARM: zynq: Enable pinctrl	2015-01-12 08:29:17 +01:00
Makefile	ARM: zynq: Actually remove hotplug.c	2014-10-20 20:53:26 +02:00
Makefile.boot	ARM: 7022/1: allow to detect conflicting zreladdrs	2011-10-17 09:12:40 +01:00
platsmp.c	ARM: v7 setup function should invalidate L1 cache	2015-06-01 11:30:26 +01:00
pm.c	ARM: zynq: PM: Fixed simple typo.	2015-01-29 15:38:09 +01:00
slcr.c	ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart	2015-05-18 14:46:37 +02:00