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8cc7236148
The Sound Blaster X-Fi driver supports Creative solutions based on 20K1 and 20K2 chipsets. Supported hardware : Creative Sound Blaster X-Fi Titanium Fatal1ty® Champion Series Creative Sound Blaster X-Fi Titanium Fatal1ty Professional Series Creative Sound Blaster X-Fi Titanium Professional Audio Creative Sound Blaster X-Fi Titanium Creative Sound Blaster X-Fi Elite Pro Creative Sound Blaster X-Fi Platinum Creative Sound Blaster X-Fi Fatal1ty Creative Sound Blaster X-Fi XtremeGamer Creative Sound Blaster X-Fi XtremeMusic Current release features: * ALSA PCM Playback * ALSA Record * ALSA Mixer Note: * External I/O modules detection not included. Signed-off-by: Wai Yew CHAY <wychay@ctl.creative.com> Singed-off-by: Ryan RICHARDS <ryan_richards@creativelabs.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
86 lines
3.0 KiB
C
86 lines
3.0 KiB
C
/**
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* Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
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*
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* This source file is released under GPL v2 license (no other versions).
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* See the COPYING file included in the main directory of this source
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* distribution for the license terms and conditions.
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*/
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#ifndef _20K2REGISTERS_H_
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#define _20K2REGISTERS_H_
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/* Timer Registers */
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#define TIMER_TIMR 0x1B7004
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#define INTERRUPT_GIP 0x1B7010
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#define INTERRUPT_GIE 0x1B7014
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/* I2C Registers */
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#define I2C_IF_ADDRESS 0x1B9000
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#define I2C_IF_WDATA 0x1B9004
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#define I2C_IF_RDATA 0x1B9008
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#define I2C_IF_STATUS 0x1B900C
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#define I2C_IF_WLOCK 0x1B9010
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/* Global Control Registers */
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#define GLOBAL_CNTL_GCTL 0x1B7090
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/* PLL Registers */
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#define PLL_CTL 0x1B7080
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#define PLL_STAT 0x1B7084
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#define PLL_ENB 0x1B7088
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/* SRC Registers */
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#define SRC_CTL 0x1A0000 /* 0x1A0000 + (256 * Chn) */
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#define SRC_CCR 0x1A0004 /* 0x1A0004 + (256 * Chn) */
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#define SRC_IMAP 0x1A0008 /* 0x1A0008 + (256 * Chn) */
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#define SRC_CA 0x1A0010 /* 0x1A0010 + (256 * Chn) */
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#define SRC_CF 0x1A0014 /* 0x1A0014 + (256 * Chn) */
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#define SRC_SA 0x1A0018 /* 0x1A0018 + (256 * Chn) */
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#define SRC_LA 0x1A001C /* 0x1A001C + (256 * Chn) */
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#define SRC_CTLSWR 0x1A0020 /* 0x1A0020 + (256 * Chn) */
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#define SRC_CD 0x1A0080 /* 0x1A0080 + (256 * Chn) + (4 * Regn) */
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#define SRC_MCTL 0x1A012C
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#define SRC_IP 0x1A102C /* 0x1A102C + (256 * Regn) */
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#define SRC_ENB 0x1A282C /* 0x1A282C + (256 * Regn) */
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#define SRC_ENBSTAT 0x1A202C
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#define SRC_ENBSA 0x1A232C
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#define SRC_DN0Z 0x1A0030
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#define SRC_DN1Z 0x1A0040
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#define SRC_UPZ 0x1A0060
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/* GPIO Registers */
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#define GPIO_DATA 0x1B7020
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#define GPIO_CTRL 0x1B7024
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/* Virtual memory registers */
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#define VMEM_PTPAL 0x1C6300 /* 0x1C6300 + (16 * Chn) */
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#define VMEM_PTPAH 0x1C6304 /* 0x1C6304 + (16 * Chn) */
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#define VMEM_CTL 0x1C7000
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/* Transport Registers */
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#define TRANSPORT_ENB 0x1B6000
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#define TRANSPORT_CTL 0x1B6004
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#define TRANSPORT_INT 0x1B6008
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/* Audio IO */
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#define AUDIO_IO_AIM 0x1B5000 /* 0x1B5000 + (0x04 * Chn) */
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#define AUDIO_IO_TX_CTL 0x1B5400 /* 0x1B5400 + (0x40 * Chn) */
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#define AUDIO_IO_TX_CSTAT_L 0x1B5408 /* 0x1B5408 + (0x40 * Chn) */
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#define AUDIO_IO_TX_CSTAT_H 0x1B540C /* 0x1B540C + (0x40 * Chn) */
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#define AUDIO_IO_RX_CTL 0x1B5410 /* 0x1B5410 + (0x40 * Chn) */
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#define AUDIO_IO_RX_SRT_CTL 0x1B5420 /* 0x1B5420 + (0x40 * Chn) */
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#define AUDIO_IO_MCLK 0x1B5600
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#define AUDIO_IO_TX_BLRCLK 0x1B5604
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#define AUDIO_IO_RX_BLRCLK 0x1B5608
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/* Mixer */
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#define MIXER_AMOPLO 0x130000 /* 0x130000 + (8 * Chn) [4095 : 0] */
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#define MIXER_AMOPHI 0x130004 /* 0x130004 + (8 * Chn) [4095 : 0] */
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#define MIXER_PRING_LO_HI 0x188000 /* 0x188000 + (4 * Chn) [4095 : 0] */
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#define MIXER_PMOPLO 0x138000 /* 0x138000 + (8 * Chn) [4095 : 0] */
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#define MIXER_PMOPHI 0x138004 /* 0x138004 + (8 * Chn) [4095 : 0] */
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#define MIXER_AR_ENABLE 0x19000C
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#endif
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