mirror of
https://github.com/edk2-porting/linux-next.git
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9ce2746304
Re-parenting to intermediate clock is supported now by the clock driver and thus there is no need in a customized CPUFreq driver, all that code is common for both Tegra20 and Tegra30. The available CPU freqs are now specified in device-tree in a form of OPPs, all users should update their device-trees. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
117 lines
2.8 KiB
C
117 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
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*/
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#include <linux/bits.h>
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/types.h>
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#include <soc/tegra/common.h>
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#include <soc/tegra/fuse.h>
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static bool cpu0_node_has_opp_v2_prop(void)
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{
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struct device_node *np = of_cpu_device_node_get(0);
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bool ret = false;
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if (of_get_property(np, "operating-points-v2", NULL))
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ret = true;
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of_node_put(np);
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return ret;
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}
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static int tegra20_cpufreq_probe(struct platform_device *pdev)
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{
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struct platform_device *cpufreq_dt;
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struct opp_table *opp_table;
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struct device *cpu_dev;
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u32 versions[2];
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int err;
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if (!cpu0_node_has_opp_v2_prop()) {
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dev_err(&pdev->dev, "operating points not found\n");
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dev_err(&pdev->dev, "please update your device tree\n");
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return -ENODEV;
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}
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if (of_machine_is_compatible("nvidia,tegra20")) {
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versions[0] = BIT(tegra_sku_info.cpu_process_id);
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versions[1] = BIT(tegra_sku_info.soc_speedo_id);
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} else {
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versions[0] = BIT(tegra_sku_info.cpu_process_id);
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versions[1] = BIT(tegra_sku_info.cpu_speedo_id);
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}
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dev_info(&pdev->dev, "hardware version 0x%x 0x%x\n",
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versions[0], versions[1]);
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cpu_dev = get_cpu_device(0);
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if (WARN_ON(!cpu_dev))
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return -ENODEV;
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opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2);
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err = PTR_ERR_OR_ZERO(opp_table);
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if (err) {
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dev_err(&pdev->dev, "failed to set supported hw: %d\n", err);
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return err;
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}
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cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
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err = PTR_ERR_OR_ZERO(cpufreq_dt);
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if (err) {
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dev_err(&pdev->dev,
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"failed to create cpufreq-dt device: %d\n", err);
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goto err_put_supported_hw;
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}
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platform_set_drvdata(pdev, cpufreq_dt);
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return 0;
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err_put_supported_hw:
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dev_pm_opp_put_supported_hw(opp_table);
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return err;
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}
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static int tegra20_cpufreq_remove(struct platform_device *pdev)
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{
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struct platform_device *cpufreq_dt;
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struct opp_table *opp_table;
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cpufreq_dt = platform_get_drvdata(pdev);
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platform_device_unregister(cpufreq_dt);
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opp_table = dev_pm_opp_get_opp_table(get_cpu_device(0));
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dev_pm_opp_put_supported_hw(opp_table);
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dev_pm_opp_put_opp_table(opp_table);
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return 0;
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}
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static struct platform_driver tegra20_cpufreq_driver = {
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.probe = tegra20_cpufreq_probe,
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.remove = tegra20_cpufreq_remove,
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.driver = {
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.name = "tegra20-cpufreq",
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},
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};
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module_platform_driver(tegra20_cpufreq_driver);
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MODULE_ALIAS("platform:tegra20-cpufreq");
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MODULE_AUTHOR("Colin Cross <ccross@android.com>");
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MODULE_DESCRIPTION("NVIDIA Tegra20 cpufreq driver");
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MODULE_LICENSE("GPL");
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